A54SX32A-PQG208 Actel, A54SX32A-PQG208 Datasheet - Page 45

• Manufacturer Part Number: A54SX32A-PQG208
• Description: FPGA - Field Programmable Gate Array 48K System Gates
• Manufacturer: Actel

Specifications of A54SX32A-PQG208

• Processor Series: A54SX32
• Core: IP Core
• Number Of Macrocells: 1800
• Maximum Operating Frequency: 350 MHz
• Number Of Programmable I/os: 249
• Delay Time: 4 ns to 8.4 ns
• Supply Voltage (max): 5.25 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.25 V
• Number Of Gates: 32 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-20 • A54SX08A Timing Characteristics
Parameter
5 V PCI Output Module Timing
t
t
t
t
t
t
d
d
5 V TTL Output Module Timing
t
t
t
t
t
t
t
t
d
d
d
Notes:
1. Delays based on 50 pF loading.
2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the V
3. Delays based on 35 pF loading.
DLH
DHL
ENZL
ENZH
ENLZ
ENHZ
DLH
DHL
DHLS
ENZL
ENZLS
ENZH
ENLZ
ENHZ
TLH
THL
TLH
THL
THLS
Slew Rate [V/ns] = (0.1*V
where C
2
2
d
load
T[LH|HL|HLS]
(Worst-Case Commercial Conditions V
is the load capacitance driven by the I/O in pF
Data-to-Pad Low to High
Data-to-Pad High to Low
Enable-to-Pad, Z to L
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
Delta Low to High
Delta High to Low
Data-to-Pad Low to High
Data-to-Pad High to Low
Data-to-Pad High to Low—low slew
Enable-to-Pad, Z to L
Enable-to-Pad, Z to L—low slew
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
Delta Low to High
Delta High to Low
Delta High to Low—low slew
is the worst case delta value from the datasheet in ns/pF.
CCI
Description
– 0.9*V
1
3
CCI)
/ (C
load
* d
T[LH|HL|HLS]
CCA
= 2.25 V, V
Min.
–2 Speed
)
v5.3
Max.
0.016
0.017
0.029
0.046
0.03
2.4
3.2
1.5
2.4
3.5
3.2
2.4
3.2
7.6
2.4
8.4
2.4
4.2
3.2
CCI
= 4.75 V, T
Min.
–1 Speed
Max.
0.032
0.017
0.031
0.057
J
0.02
2.8
3.6
1.7
2.8
3.9
3.6
2.8
3.6
8.6
2.7
9.5
2.8
4.7
3.6
= 70°C)
Min.
Std. Speed
CCI
value into the following equation:
Max.
0.022
0.023
0.037
0.066
0.04
10.1
11.0
3.2
4.2
2.0
3.2
4.6
4.2
3.2
4.2
3.2
3.2
5.6
4.2
Min.
–F Speed
SX-A Family FPGAs
Max.
0.032
0.052
0.031
0.051
0.089
14.2
15.4
4.5
5.9
2.8
4.5
6.4
5.9
4.5
5.9
4.5
4.5
7.8
5.9
Units
ns/pF
ns/pF
ns/pF
ns/pF
ns/pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-25