LFXP2-17E-5FTN256C Lattice, LFXP2-17E-5FTN256C Datasheet - Page 27

• Manufacturer Part Number: LFXP2-17E-5FTN256C
• Description: FPGA - Field Programmable Gate Array 17K LUTs 201I/O DSP 1.2V -5 Speed
• Manufacturer: Lattice

Specifications of LFXP2-17E-5FTN256C

• Number Of Macrocells: 17000
• Maximum Operating Frequency: 200 MHz
• Number Of Programmable I/os: 201
• Data Ram Size: 35 Kbit
• Supply Voltage (max): 1.14 V
• Supply Current: 28 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.26 V
• Package / Case: FTBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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register. Similarly, CE and RST are selected from their four respective sources (CE0, CE1, CE2, CE3 and RST0,
RST1, RST2, RST3) at each input register, pipeline register and output register.
Signed and Unsigned with Different Widths
The DSP block supports other widths, in addition to x9, x18 and x36 widths, of signed and unsigned multipliers. For
unsigned operands, unused upper data bits should be filled to create a valid x9, x18 or x36 operand. For signed
two’s complement operands, sign extension of the most significant bit should be performed until x9, x18 or x36
width is reached. Table 2-7 provides an example of this.
Table 2-7. Sign Extension Example
OVERFLOW Flag from MAC
The sysDSP block provides an overflow output to indicate that the accumulator has overflowed. “Roll-over” occurs
and an overflow signal is indicated when any of the following is true: two unsigned numbers are added and the
result is a smaller number than the accumulator, two positive numbers are added with a negative sum or two nega-
tive numbers are added with a positive sum. Note that when overflow occurs the overflow flag is present for only
one cycle. By counting these overflow pulses in FPGA logic, larger accumulators can be constructed. The condi-
tions for the overflow signal for signed and unsigned operands are listed in Figure 2-24.
Figure 2-24. Accumulator Overflow/Underflow
Number
+5
-6
Unsigned
Overflow signal is generated
0101
N/A
for one cycle when this
boundary is crossed
000000101
Unsigned
9-bit
N/A
011111100
011111101
011111110
011111111
100000000
100000001
100000010
000000000000000101
011111100
011111101
011111110
011111111
100000000
100000001
100000010
Unsigned
Unsigned Operation
18-bit
Signed Operation
N/A
256
257
258
255
-256
-255
-254
254
255
252
253
254
252
253
2-24
000000001
111111111
111111110
111111101
000000001
111111111
111111110
111111101
000000011
000000010
000000000
000000011
000000010
000000000
Signed
1010
0101
Two’s Complement
+3
+2
+1
-1
-2
-3
511
510
509
0
3
2
1
0
Signed 9 Bits
LatticeXP2 Family Data Sheet
000000101
111111010
Carry signal is generated for
boundary is crossed
one cycle when this
111111111111111010
000000000000000101
Two’s Complement
Signed 18 Bits
Architecture