A3P1000L-FGG484 Actel, A3P1000L-FGG484 Datasheet - Page 137

• Manufacturer Part Number: A3P1000L-FGG484
• Description: FPGA - Field Programmable Gate Array 1M SYSTEM GATES
• Manufacturer: Actel

Specifications of A3P1000L-FGG484

• Processor Series: A3P1000
• Core: IP Core
• Maximum Operating Frequency: 781.25 MHz
• Number Of Programmable I/os: 300
• Data Ram Size: 147456
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 1 M
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-200 • A3P600L Global Resource – Applies to 1.5 V DC Core Voltage
Table 2-201 • A3P600L Global Resource – Applies to 1.2 V DC Core Voltage
Parameter
t
t
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
3. For specific junction temperature and voltage supply levels, refer to
Parameter
t
t
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
3. For specific junction temperature and voltage supply levels, refer to
RCKL
RCKH
RCKMPWH
RCKMPWL
RCKSW
RCKL
RCKH
RCKMPWH
RCKMPWL
RCKSW
RMAX
RMAX
element, located in a lightly loaded row (single element is connected to the global net).
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
values.
element, located in a lightly loaded row (single element is connected to the global net).
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
values.
Input Low Delay for Global Clock
Input High Delay for Global Clock
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Input Low Delay for Global Clock
Input High Delay for Global Clock
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Commercial-Case Conditions: T
Commercial-Case Conditions: T
Description
Description
R e v i s i o n 9
J
J
= 70°C, VCC = 1.425 V
= 70°C, VCC = 1.14 V
Min.
Min.
0.90
0.89
1.48
1.47
Table 2-6 on page 2-7
Table 2-6 on page 2-7
ProASIC3L Low Power Flash FPGAs
1
1
–1
–1
Max.
Max.
1.14
1.17
0.28
1.76
1.80
0.33
2
2
Min.
Min.
1.06
1.04
1.74
1.72
Std.
1
Std.
1
Max.
Max.
1.34
1.38
0.33
2.07
0.39
2.11
for derating
for derating
2
2
Units
Units
MHz
MHz
2- 123
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns