AD5541ABRMZ Analog Devices Inc, AD5541ABRMZ Datasheet - Page 5

• Manufacturer Part Number: AD5541ABRMZ
• Description: IC DAC 16BIT 2.7-5.5V 10-MSOP
• Manufacturer: Analog Devices Inc
• Series: nanoDAC™r

Specifications of AD5541ABRMZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Settling Time: 1µs
• Number Of Bits: 16
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 825W
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Resolution (bits): 16bit
• Sampling Rate: 1MSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 2.7V To 5.5V
• Supply Current: 125µA
• Digital Ic Case Style: MSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS
V
noted.
Table 4.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
SCLK
1
2
3
4
5
6
7
8
9
9
10
11
12
Guaranteed by design and characterization. Not production tested.
All input signals are specified with t
DD
= 5 V, 2.5 V ≤ V
1,2
SCLK
LDAC
DIN
CS
Limit at
1.8 ≤ V
14
70
35
35
5
5
5
10
35
5
5
20
10
15
REF
≤ V
LOGIC
DD
t
12
, V
≤ 2.7 V
R
t
= t
6
INH
F
= 1 ns/V and timed from a voltage level of (V
t
DB15
t
4
= 90% of V
8
t
9
Limit at
2.7 V ≤ V
50
20
10
10
5
5
5
5
10
4
5
20
10
15
LOGIC
LOGIC
, V
INL
t
2
≤ 5.5 V
= 10% of V
Figure 3. Timing Diagram
Rev. A | Page 5 of 20
t
1
t
3
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
LOGIC
INL
, AGND = DGND = 0 V, −40°C < T
+ V
INH
)/2.
t
7
t
Description
SCLK cycle frequency
SCLK cycle time
SCLK high time
SCLK low time
CS low to SCLK high setup
CS high to SCLK high setup
SCLK high to CS low hold time
SCLK high to CS high hold time
Data setup time
Data hold time (V
Data hold time (V
LDAC pulse width
CS high to LDAC low setup
CS high time between active periods
5
t
11
t
10
INH
INH
= 90% of V
= 3 V, V
A
INL
< +105°C, unless otherwise
= 0 V)
DD
, V
INL
= 10% of V
AD5541A
DD
)