STM8L101G3U6 STMicroelectronics, STM8L101G3U6 Datasheet - Page 80

• Manufacturer Part Number: STM8L101G3U6
• Description: IC MCU 8BIT 8KB FLASH 28UFQFPN
• Manufacturer: STMicroelectronics
• Series: STM8L EnergyLiter

Specifications of STM8L101G3U6

• Featured Product: STM32 Cortex-M3 Companion Products
• Core Processor: STM8
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Infrared, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-UFQFN
• Processor Series: STM8L10x
• Core: STM8
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 3
• Operating Supply Voltage: 1.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWSTM8
• Minimum Operating Temperature: - 40 C
• Data Converters: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Revision history
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Table 44.
14-Oct-2010
21-Jul-2010
Date
Document revision history (continued)
Revision
10
11
Modified
Table 4: STM8L101xx pin description on page 20
and PB4)
Modified
Current characteristics on page 39
Modified V
Added notes below UFQFPN32 package
Added STM8L101F1 devices:
Modifed text above
configuration on page 56
Modified
Doc ID 15275 Rev 11
Modified
features on page 8
addresses on page 24
Modified warning below
STM8L101xx pin description on page 20
Modified
page 73
Table 3: Legend/abbreviation for table 4 on page 20
Table 13: Voltage characteristics on page 38
Figure 32 on page 56
IH
Table 1: Device summary on page
Figure 47: STM8L101xx ordering information scheme on
in
Table 26: I/O static characteristics on page 50
Figure 32: Recommended NRST pin
and
Table 5: Flash and RAM boundary
Figure 3 on page 15
Changes
1,
and
Table 2: Device
(for PA0, PA1, PB0
belowTable 4:
STM8L101xx
and
Table 14:
and