AD9235-65PCB Analog Devices Inc, AD9235-65PCB Datasheet

BOARD EVAL FOR AD9235-65

AD9235-65PCB

Manufacturer Part Number
AD9235-65PCB
Description
BOARD EVAL FOR AD9235-65
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9235-65PCB

Rohs Status
RoHS non-compliant
Number Of Adc's
1
Number Of Bits
12
Sampling Rate (per Second)
65M
Data Interface
Parallel
Inputs Per Adc
1 Differential
Input Range
2 Vpp
Power (typ) @ Conditions
320mW @ 65MSPS
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
AD9235-65
FEATURES
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 70 dBc to Nyquist at 65 MSPS
SFDR = 85 dBc to Nyquist at 65 MSPS
Low power: 300 mW at 65 MSPS
Differential input with 500 MHz bandwidth
On-chip reference and SHA
DNL = ±0.4 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
APPLICATIONS
Ultrasound equipment
IF sampling in communications receivers
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
GENERAL DESCRIPTION
The AD9235 is a family of monolithic, single 3 V supply, 12-bit,
20/40/65 MSPS analog-to-digital converters (ADCs). This
family features a high performance sample-and-hold amplifier
(SHA) and voltage reference. The AD9235 uses a multistage
differential pipelined architecture with output error correction
logic to provide 12-bit accuracy at 20/40/65 MSPS data rates
and guarantee no missing codes over the full operating
temperature range.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and offsets including single-ended
applications. It is suitable for multiplexed systems that switch
full-scale voltage levels in successive channels and for sampling
single-channel inputs at frequencies well beyond the Nyquist
rate. Combined with power and cost savings over previously
available ADCs, the AD9235 is suitable for applications in
communications, imaging, and medical ultrasound.
A single-ended clock input is used to control all internal
conversion cycles. A duty cycle stabilizer (DCS) compensates
for wide variations in the clock duty cycle while maintaining
excellent overall ADC performance. The digital output data is
presented in straight binary or twos complement formats. An
out-of-range (OTR) signal indicates an overflow condition that
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
IS-95, CDMA-One, IMT-2000
can be used with the most significant bit to determine low or
high overflow.
Fabricated on an advanced CMOS process, the AD9235 is avail-
able in a 28-lead TSSOP and a 32-lead LFCSP and is specified
over the industrial temperature range (–40°C to +85°C).
PRODUCT HIGHLIGHTS
1. The AD9235 operates from a single 3 V power supply and
2. Operating at 65 MSPS, the AD9235 consumes a low 300 mW.
3. The patented SHA input maintains excellent performance for
4. The AD9235 pinout is similar to the AD9214-65, a 10-bit,
5. The clock DCS maintains overall ADC performance over a
6. The OTR output bit indicates when the signal is beyond the
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
SENSE
REFB
VREF
REFT
VIN+
VIN–
features a separate digital output driver supply to accommo-
date 2.5 V and 3.3 V logic families.
input frequencies up to 100 MHz and can be configured for
single-ended or differential operation.
65 MSPS ADC. This allows a simplified upgrade path from
10 bits to 12 bits for 65 MSPS systems.
wide range of clock pulse widths.
selected input range.
SHA
SELECT
REF
FUNCTIONAL BLOCK DIAGRAM
12-Bit, 20/40/65 MSPS
AGND
AVDD
A/D
© 2004 Analog Devices, Inc. All rights reserved.
0.5V
MDAC1
DUTY CYCLE
STABILIZER
AD9235
CLOCK
4
CLK
3 V A/D Converter
Figure 1.
CORRECTION LOGIC
OUTPUT BUFFERS
PIPELINE
PDWN
8-STAGE
1 1/2-BIT
16
12
DRVDD
SELECT
MODE
MODE
www.analog.com
AD9235
A/D
DGND
3
OTR
D11
D0

Related parts for AD9235-65PCB

AD9235-65PCB Summary of contents

Page 1

... The AD9235 operates from a single 3 V power supply and features a separate digital output driver supply to accommo- date 2.5 V and 3.3 V logic families. 2. Operating at 65 MSPS, the AD9235 consumes a low 300 mW. 3. The patented SHA input maintains excellent performance for input frequencies up to 100 MHz and can be configured for single-ended or differential operation ...

Page 2

... Changes to Absolute Maximum Ratings ........................................5 Changes to Ordering Guide .............................................................5 Changes to Pin Function Descriptions...........................................6 New Definitions of Specifications Section .....................................7 Changes to TPCs 1 to 12...................................................................9 Changes to Theory of Operation Section.................................... 13 Applying the AD9235 .................................................................... 15 Theory of Operation.................................................................. 15 Analog Input ............................................................................... 15 Clock Input Considerations...................................................... 16 Power Dissipation and Standby Mode .................................... 17 Digital Outputs ........................................................................... 18 Voltage Reference ....................................................................... 18 Operational Mode Selection ...

Page 3

... IV 2.25 3.0 3.6 2. ±0. 110 V 1.0 Rev Page AD9235 MIN MAX AD9235BRU/BCP-65 Typ Max Min Typ Max 12 12 ±0.50 ±1.20 ±0.50 ±1.20 ±0.50 ±2.50 ±0.50 ±2.60 ±0.35 ±0.75 ±0.40 ±0.80 ±0.35 ±0.35 ±0.50 ±0.90 ±0.70 ±1.30 ±0.40 ±0.45 ± ...

Page 4

... Full OUT-OF-RANGE RECOVERY TIME Full 1 For the AD9235-65 model only, with duty cycle stabilizer enabled. DCS function not applicable for -20 and -40 models. 2 Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output. 3 Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB. ...

Page 5

... AD9235 MIN MAX Max Unit dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc ...

Page 6

... INPUT AD9235BRU/BCP-20 AD9235BRU/BCP-40 Test Level Min Typ Max Min V 92.0 IV 80.0 88.5 I 91 84.0 Rev Page AD9235BRU/BCP-65 Typ Max Min Typ Max 92.0 92.0 89.0 90.0 74.0 83.0 85.0 85.0 80.5 Unit dBc dBc dBc dBc dBc dBc dBc dBc ...

Page 7

... Sample tested only. Parameter is guaranteed by design and characteriza- tion testing. Parameter is a typical value only. 100% production tested at 25°C; guaranteed by de- sign and characterization testing for industrial tem- perature range; 100% production tested at tempera- ture extremes for military devices. AD9235 ...

Page 8

... Data Output Bits. Digital Output Ground. Digital Output Driver Supply. Must be decoupled to DGND with a minimum. 0.1 µF capacitor. Recommended decoupling is 0.1 µF in parallel with 10 µF. Do Not Connect. Rev Page VREF 24 PIN 1 SENSE INDICATOR 23 MODE 22 OTR 21 AD9235 D11(MSB) 20 TOP VIEW D10 19 (Not to Scale ...

Page 9

... Out-of-Range Recovery Time The time it takes for the ADC to reacquire the analog input after a transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. Rev Page AD9235 ...

Page 10

... AD9235 EQUIVALENT CIRCUITS AVDD VIN+, VIN– Figure 5. Equivalent Analog Input Circuit AVDD MODE 20kΩ Figure 6. Equivalent MODE Input Circuit DRVDD Figure 7. Equivalent Digital Output Circuit AVDD CLK, PDWN Figure 8. Equivalent Digital Input Circuit Rev Page D11–D0, OTR ...

Page 11

... MHz IN SNR = 69.4dBc SINAD = 69.1dBc ENOB = 11.2 BITS THD = –81.0dBc SFDR = 83.8dBc 84.5 91 MHz Figure 13. AD9235-40: Single Tone SNR/SFDR vs SNR = 68.5dBc SINAD = 66.5dBc ENOB = 10.8 BITS THD = –71.0dBc SFDR = 71.2dBc 123.5 130.0 = 100 MHz Figure 14. AD9235-20: Single Tone SNR/SFDR vs Rev Page − ...

Page 12

... SNR SINGLE-ENDED (dBFS) 60 SNR DIFFERENTIAL (dBc) 50 SNR SINGLE-ENDED (dBc) 40 –30 –25 –20 –15 A (dBFS) IN Figure 16. AD9235-40: Single Tone SNR/SFDR vs. A 100 SFDR DIFFERENTIAL (dBFS) SFDR 90 DIFFERENTIAL (dBc) SFDR SINGLE-ENDED (dBFS) 80 SNR SINGLE-ENDED(dBc) DIFFERENTIAL (dBFS) 70 SNR SINGLE-ENDED (dBFS) 60 SNR DIFFERENTIAL(dBc) 50 SNR ...

Page 13

... MHz IN2 Figure 25. Dual Tone SNR/SFDR vs 156.0 162.0 –24 = 145 MHz IN2 Figure 26. Dual Tone SNR/SFDR vs. A Rev Page AD9235 2V SFDR 1V SFDR 2V SNR 1V SNR –21 –18 –15 –12 –9 A (dBFS) IN with MHz and MHz IN IN1 IN2 2V SFDR 1V SFDR 2V SNR 1V SNR – ...

Page 14

... AD9235 75 AD9235-40: AD9235-20 SINAD 2V SINAD 69 AD9235-20: AD9235-40: 1V SINAD 1V SINAD 66 AD9235-65: 1V SINAD SAMPLE RATE (MSPS) Figure 27. SINAD vs. f with f CLK 90 SFDR: DCS ON 80 SFDR: DCS OFF SINAD: DCS ON 70 SINAD: DCS OFF DUTY CYCLE (%) Figure 28. SINAD/SFDR vs. Clock Duty Cycle 90 SFDR 2V DIFF 85 80 ...

Page 15

... APPLYING THE AD9235 THEORY OF OPERATION The AD9235 architecture consists of a front end SHA followed by a pipelined switched capacitor ADC. The pipelined ADC is divided into three sections, consisting of a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stages ...

Page 16

... VIN– range of clock input duty cycles without affecting the perform- AGND ance of the AD9235. As shown in Figure 30, noise and distor- tion performance are nearly flat over a 30% range of duty cycle. The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge result, any changes to the sampling frequency require approximately 100 clock cycles to allow the DLL to acquire and lock to the new rate ...

Page 17

... POWER DISSIPATION AND STANDBY MODE As shown in Figure 38, the power dissipated by the AD9235 is proportional to its sample rate. The digital power dissipation does not vary substantially between the three speed grades because it is determined primarily by the strength of the digital drivers and the load on each output bit ...

Page 18

... AD9235; these transients can detract from the converter’s dynamic performance. The lowest typical conversion rate of the AD9235 is 1 MSPS. At clock rates below 1 MSPS, dynamic performance may degrade. VOLTAGE REFERENCE A stable and accurate 0.5 V voltage reference is built into the AD9235 ...

Page 19

... The input span is always twice the value of the reference voltage; therefore, the external reference must be limited to a maximum the internal reference of the AD9235 is used to drive multiple converters to improve gain matching, the loading of the refer- ence by the other converters must be considered. Figure 42 depicts how the internal reference voltage is affected by loading ...

Page 20

... AD9235 LFCSP EVALUATION BOARD The typical bench setup used to evaluate the ac performance of the AD9235 is similar to the TSSOP Evaluation Board connections (refer to the schematics for connection details). The AD9235 can be driven single-ended or differentially through a transformer. Separate power pins are provided to isolate the DUT from the support circuitry. Each input configuration can be selected by proper connection of various jumpers (refer to the schematics) ...

Page 21

... FBEAD FBEAD FBEAD FBEAD Figure 44. TSSOP Evaluation Board Schematic, DUT + + + AVDD + Rev Page AD9235 ...

Page 22

... AD9235 AUXCLK T1– R11 4 3 49.9Ω T2 MC100LVEL33D 8 U3 AVDD VCC NC 7 OUT INA 6 REF INB 5 VEE INCOM AVDD AVDD AVDD R12 R13 C27 U8 DECOUPLING 113Ω 113Ω 0.1µF C26 0.1µF R14 R15 90Ω 90Ω JP9 R19 R2 R18 500Ω ...

Page 23

... C56 ACOM 20 0.1µF COMP1 19 FSADJ 18 REFIO 17 REFLO 16 C51 C49 R30 0.1µF 0.1µF 2kΩ SLEEP 15 Rev Page AD9235 JP42 JP40 C44 R21 15pF JP45 22Ω VIN+ C44B R22 JP46 22Ω VIN– JP41 C43 15pF JP43 AVDD R16 1kΩ ...

Page 24

... AD9235 Figure 48. TSSOP Evaluation Board Layout, Primary Side Rev Page ...

Page 25

... Figure 49. TSSOP Evaluation Board Layout, Secondary Side Rev Page AD9235 ...

Page 26

... AD9235 Figure 50. TSSOP Evaluation Board Layout, Ground Plane Rev Page ...

Page 27

... Figure 51. TSSOP Evaluation Board Power Plane Rev Page AD9235 ...

Page 28

... AD9235 Figure 52. TSSOP Evaluation Board Layout, Primary Silkscreen Rev Page ...

Page 29

... Figure 53. TSSOP Evaluation Board Layout, Secondary Silkscreen Rev Page AD9235 ...

Page 30

... Figure 54. LFCSP Evaluation Board Schematic, Analog Inputs and DUT Rev Page GND MODE 0.1µF 3 GND OVERRANGE BIT (MSB REFB DRVDD 16 7 DRVDD DGND 15 8 GND D7 14 RP2 220Ω AD9235 AGND VIN VIN– AGND AVDD (LSB RP1 220Ω CLK R8 1kΩ P14 P13 GND ...

Page 31

... Figure 55. LFCSP Evaluation Board Schematic, Digital Path DRY DRVDD DRVDD R38 R39 1kΩ 1kΩ VAMP C44 VAMP 0.1µF GND AD8351 U3 PWDN VOCM 1 10 RGP1 VPOS 2 9 INHI OPH1 3 8 INLO OPLO 4 7 RPG2 COMM 5 6 GND R34 1.2kΩ Rev Page AD9235 HEADER GND MSB GND ...

Page 32

... AD9235 Figure 56. LFCSP Evaluation Board Schematic, Clock Input Rev Page ...

Page 33

... Figure 57. LFCSP Evaluation Board Layout, Primary Side Figure 58. LFCSP Evaluation Board Layout, Secondary Side Figure 59. LFCSP Evaluation Board Layout, Ground Plane Figure 60. LFCSP Evaluation Board Layout, Power Plane Rev Page AD9235 ...

Page 34

... AD9235 Figure 61. LFCSP Evaluation Board Layout, Primary Silkscreen Figure 62. LFCSP Evaluation Board Layout, Secondary Silkscreen Rev Page ...

Page 35

... Chip Resistor 0603 Chip Resistor 0603 Chip Resistor 0603 Resistor Pack R_742 ADT1-1WT AWT1-1T 74LVTH162374 TSSOP-48 CMOS Register AD9235BCP ADC (DUT) LFCSP-32 74VCX86M SOIC-14 AD92XXBCP/PCB PCB AD8351 Op Amp MSOP-8 MACOM Transformer ETC1-1-13 1-1 TX Chip Resistor 0603 Chip Resistor 0603 Chip Resistor ...

Page 36

... AD9235 OUTLINE DIMENSIONS PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE 9.80 9.70 9. 4.50 4.40 4. PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.20 SEATING COPLANARITY 0.19 0.09 PLANE 0.10 COMPLIANT TO JEDEC STANDARDS MO-153AE Figure 63. 28-Lead Thin Shrink Small Outline Package [TSSOP] ...

Page 37

... AD9235BCPZ-65 –40°C to +85° AD9235BCPZRL7-65 –40°C to +85°C AD9235-20PCB AD9235-40PCB AD9235-65PCB AD9235BCP-20EB AD9235BCP-40EB AD9235BCP-65EB Pb-free part recommended that the exposed paddle be soldered to the ground plane. There is an increased reliability of the solder joints and maximum thermal capability of the package is achieved with exposed paddle soldered to the customer board. ...

Page 38

... AD9235 NOTES Rev Page ...

Page 39

... NOTES Rev Page AD9235 ...

Page 40

... AD9235 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02461–0–10/04(C) Rev Page ...

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