AT32UC3L0-XPLD Atmel, AT32UC3L0-XPLD Datasheet

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... SPI Slaves can be Addressed • Two Master and Two Slave Two-wire Interface (TWI), 400kbit/s I • One 8-channel Analog-to-digital Converter (ADC) with Bits Resolution – Internal Temperature Sensor ® ® 32-bit AVR Microcontroller 2 C-compatible ® 32-bit AVR Microcontroller AT32UC3L064 AT32UC3L032 AT32UC3L016 Preliminary 32099F–11/2010 ...

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... Single-pin Programming Trace and Debug Interface Muxed with Reset Pin ™ – NanoTrace Provides Trace Capabilities through JTAG or aWire Interface • 48-pin TQFP/QFN/TLLGA (36 GPIO Pins) • Five High-drive I/O Pins • Single 1.62-3.6 V Power Supply 32099F–11/2010 ® ® ® ® QTouch and Atmel AVR QMatrix AT32UC3L016/32/64 ® Touch Acquisition 2 ...

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... The AST can operate in counter mode or calendar mode. The Frequency Meter (FREQM) allows accurate measuring of a clock frequency by comparing known reference clock. 32099F–11/2010 ® ® AVR AT32UC3L is a complete System-on-chip microcontroller based on the AT32UC3L016/32/64 3 ...

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... The NanoTrace interface enables trace feature for aWire- or JTAG-based debuggers. The sin- gle-pin aWire interface allows all features available through the JTAG interface to be accessed through the RESET pin, allowing the JTAG pins to be used for GPIO or peripherals. 32099F–11/2010 ® ® (AKS ) technology for unambiguous detection of key events. The easy-to-use AT32UC3L016/32/64 4 ...

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... INTERFACE XOUT32 OSC0 DFLL INTERRUPT CONTROLLER EXTERNAL INTERRUPT EXTINT[5..1] CONTROLLER NMI PWM CONTROLLER PWMA[35..0] ASYNCHRONOUS TIMER WATCHDOG TIMER FREQUENCY METER AT32UC3L016/32/64 LOCAL BUS INTERFACE AVR32UC CPU MEMORY PROTECTION UNIT 16/8 KB SRAM INSTR DATA INTERFACE INTERFACE 64/32/16 KB HIGH SPEED FLASH BUS MATRIX ...

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... Max Frequency Packages 32099F–11/2010 Configuration Summary AT32UC3L064 64KB 16KB Digital Frequency Locked Loop 40-150MHz (DFLL) Crystal Oscillator 3-16MHz (OSC0) Crystal Oscillator 32KHz (OSC32K) RC Oscillator 120MHz (RC120M) RC Oscillator 115kHz (RCSYS) RC Oscillator 32kHz (RC32K) TQFP48/QFN48/TLLGA48 AT32UC3L016/32/64 AT32UC3L032 AT32UC3L016 32KB 16KB 16KB 8KB ...

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... The device pins are multiplexed with peripheral functions as described in Figure 3-1. PA15 PA16 PA17 PA19 PA18 VDDIO GND PB11 GND PA10 PA12 VDDIO 32099F–11/2010 TQFP48/QFN48 Pinout AT32UC3L016/32/64 Section 3.2. 24 PA21 23 PB10 22 RESET_N 21 PB04 20 PB05 19 GND 18 VDDCORE 17 VDDIN 16 PB01 15 PA07 14 PA01 13 PA02 7 ...

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... Figure 3-2. PA16 PA17 PA19 PA18 VDDIO GND PB11 GND PA10 PA12 VDDIO 32099F–11/2010 TLLGA48 Pinout AT32UC3L016/32/64 24 PA21 23 PB10 22 RESET_N 21 PB04 20 PB05 19 GND 18 VDDCORE 17 VDDIN 16 PB01 15 PA07 14 PA01 8 ...

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... GLOC AD[1] CLK1 IN[6] ADCIFB TC0 GLOC AD[2] CLK0 IN[5] TC0 USART2 TWIMS1 A1 CTS TWD ADCIFB TC0 GLOC AD[4] B1 IN[4] AT32UC3L016/32/64 GPIO Function PWMA SCIF PWMA[0] GCLK[0] PWMA ACIFB TWIMS0 PWMA[1] ACAP[0] TWALM PWMA ACIFB USART0 PWMA[2] ACBP[0] CLK PWMA ACIFB ...

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... TC1 USART1 USART3 CLK0 TXD CLK TC1 USART1 CLK1 RXD TC1 TWIMS1 CLK2 TWALM for a description of the various peripheral signals. ”Electrical Characteristics” on page 41 AT32UC3L016/32/64 TWIMS1 PWMA TWALM PWMA[19] GLOC PWMA SCIF IN[3] PWMA[20] RC32OUT ADCIFB PWMA PWMA TRIGGER PWMA[21] PWMAOD[21] ...

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... JTAG debug port OSC0, OSC32 JTAG Pinout 48-pin Pin Name 11 PA00 14 PA01 13 PA02 4 PA03 Nexus OCD AUX Port Connections AXS=1 AXS=0 PA05 PB08 PA10 PB00 PA18 PB04 PA17 PB05 AT32UC3L016/32/64 for a description of the electrical properties JTAG Pin TCK TMS TDO TDI 11 ...

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... PA20 Table 3-6 are not mapped to the normal GPIO functions.The aWire DATA Section 6.1.4 on page 40 Other Functions 48-pin Pin 27 PA11 22 RESET_N 11 PA00 AT32UC3L016/32/64 Pin Oscillator Function XIN0 XIN32 XIN32_2 XOUT0 XOUT32 XOUT32_2 for constraints on the WAKE_N pin. Function WAKE_N aWire DATA ...

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... ADC Interface - ADCIFB Analog Output Output Input aWire - AW I/O I/O Capacitive Touch Module - CAT I/O I/O Analog Output Input Output External Interrupt Controller - EIC Input Input Glue Logic Controller - GLOC Input Output JTAG module - JTAG Input Input Output AT32UC3L016/32/64 Active Level Comments 13 ...

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... Analog Analog Analog Serial Peripheral Interface - SPI I/O I/O I/O I/O Timer/Counter - TC0, TC1 I/O I/O I/O I/O I/O I/O Input Input Input Two-wire Interface - TWIMS0, TWIMS1 I/O I/O I/O AT32UC3L016/32/64 Low Not all channels support open drain mode Low Low 14 ...

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... Power Input Power Input Ground Ground Auxiliary Port - AUX Output Output Output Input Low Output Low General Purpose I/O pin I/O I/O AT32UC3L016/32/64 Comments 1.62V to 1.98V 1.62V to 3.6V. VDDIO should always be equal to or lower than VDDIN. 1.62V to 1.98V 1.62V to 1.98V (1) 1.62V to 3.6V 15 ...

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... High-Drive Pins The five pins PA02, PA06, PA08, PA09, and PB01 have high-drive output capabilities. Refer to Section 7. on page 41 32099F–11/2010 Section 3.2.3 on page 11 for the JTAG port connections. Section 3.2 on page for electrical characteristics. AT32UC3L016/32/64 9). As required by the SMBus specification, 16 ...

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... ADC inputs, the voltage applied to the pin must not exceed 1.98V. Internal circuitry ensures that the pin cannot be used as an analog input pin when the I/O drives to VDD. When the pins are not used for ADC inputs, the pins may be driven to the full I/O voltage range. 32099F–11/2010 AT32UC3L016/32/64 17 ...

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... The larger format increases performance, allowing an addition and a data move in the same instruction in a single cycle. Load and store instructions have several different formats in order to reduce code size and speed up execution. 32099F–11/2010 AT32UC3L016/32/64 TM technology 18 ...

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... Details on which devices that are mapped into the local bus space is given in the CPU Local Bus section in the Memories chapter. Figure 4-1 on page 20 32099F–11/2010 displays the contents of AVR32UC. AT32UC3L016/32/64 19 ...

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... Figure 4-2 on page 21 32099F–11/2010 Overview of the AVR32UC CPU OCD system AVR32UC CPU pipeline High Speed High Speed Bus master shows an overview of the AVR32UC pipeline stages. AT32UC3L016/32/64 Power/ Reset control MPU Data memory controller High CPU Local Speed Bus ...

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... AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an 32099F–11/2010 The AVR32UC Pipeline Regfile IF ID Read Prefetch unit Decode unit AT32UC3L016/32/64 MUL Multiply unit Regfile ALU ALU unit write Load-store LS unit ...

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... The Architecture Revision field in the CONFIG0 system register identifies which architecture revision is implemented in a specific device. AVR32UC CPU revision 3 is fully backward-compatible with revisions 1 and 2, ie. code compiled for revision binary-compatible with revision 3 CPUs. 32099F–11/2010 Instructions with Unaligned Reference Support Supported Alignment Word Word AT32UC3L016/32/64 22 ...

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... 4-5. The lower word contains the and Q condition code flags and the R, T, The Status Register High Halfword - - - AT32UC3L016/32/64 INT2 INT3 Exception Bit 31 Bit 0 Bit 31 Bit 0 Bit 31 Bit SP_SYS SP_SYS SP_SYS R12 R12 R12 R11 R11 R11 R10 R10 R10 R9 R9 ...

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... Overview of Execution Modes, their Priorities and Privilege Levels. Mode Security Non Maskable Interrupt Privileged Exception Privileged Interrupt 3 Privileged Interrupt 2 Privileged Interrupt 1 Privileged Interrupt 0 Privileged Supervisor Privileged Application Unprivileged AT32UC3L016/32/64 Bit Bit name Initial value Carry Zero Sign Overflow Saturation Lock ...

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... Return Status Register for Debug mode 52 RAR_SUP Unused in AVR32UC 56 RAR_INT0 Unused in AVR32UC 60 RAR_INT1 Unused in AVR32UC 64 RAR_INT2 Unused in AVR32UC 68 RAR_INT3 Unused in AVR32UC 72 RAR_EX Unused in AVR32UC 76 RAR_NMI Unused in AVR32UC 80 RAR_DBG Return Address Register for Debug mode 84 JECR Unused in AVR32UC 88 JOSP Unused in AVR32UC 92 JAVA_LV0 Unused in AVR32UC AT32UC3L016/32/64 25 ...

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... MPU Address Register region 3 336 MPUAR4 MPU Address Register region 4 340 MPUAR5 MPU Address Register region 5 344 MPUAR6 MPU Address Register region 6 348 MPUAR7 MPU Address Register region 7 352 MPUPSR0 MPU Privilege Select Register region 0 356 MPUPSR1 MPU Privilege Select Register region 1 AT32UC3L016/32/64 26 ...

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... Secure State Stack Pointer System Register 436 SS_SP_APP Secure State Stack Pointer Application Register 440 SS_RAR Secure State Return Address Register 444 SS_RSR Secure State Return Status Register 448-764 Reserved Reserved for future use 768-1020 IMPL IMPLEMENTATION DEFINED Table 4-4 on page AT32UC3L016/32/64 31. Most of the handlers are 27 ...

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... Program Counter. If the rete instruction returns from INT0, INT1, INT2, or INT3, registers R8-R12 and LR are also popped from the system stack. The restored Status Register contains information allowing the core to resume operation in the previous execution mode. This concludes the event handling. 32099F–11/2010 31, is loaded into the Program Counter. AT32UC3L016/32/64 Table 4 ...

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... If several events occur on the same instruction, they are handled in a prioritized way. The priority ordering is presented in locations in the pipeline, the events on the oldest instruction are always handled before any events on any younger instruction, even if the younger instruction has events of higher priority 32099F–11/2010 AT32UC3L016/32/64 Table 4-4 on page 31. If events occur on several instructions at different 29 ...

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... An instruction B is younger than an instruction was sent down the pipeline later than A. The addresses and priority of simultaneous events are shown in the exceptions are unused in AVR32UC since it has no MMU, coprocessor interface, or floating- point unit. 32099F–11/2010 AT32UC3L016/32/64 Table 4-4 on page 31. Some of 30 ...

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... MPU DTLB Miss (Write) MPU DTLB Protection (Read) MPU DTLB Protection (Write) MPU DTLB Modified UNUSED AT32UC3L016/32/64 Stored Return Address Undefined First non-completed instruction PC of offending instruction PC of offending instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction ...

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... Internal High-Speed SRAM, Single-cycle access at full speed – 16Kbytes (AT32UC3L064, AT32UC3L032) – 8Kbytes (AT32UC3L016) 5.2 Physical Memory Map The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot ...

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... FREQM Frequency Meter - FREQM GPIO General Purpose Input/Output Controller - GPIO Universal Synchronous/Asynchronous USART0 Receiver/Transmitter - USART0 Universal Synchronous/Asynchronous USART1 Receiver/Transmitter - USART1 Universal Synchronous/Asynchronous USART2 Receiver/Transmitter - USART2 Universal Synchronous/Asynchronous USART3 Receiver/Transmitter - USART3 SPI Serial Peripheral Interface - SPI TWIM0 Two-wire Master Interface - TWIM0 AT32UC3L016/32/64 33 ...

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... Two-wire Slave Interface - TWIS0 TWIS1 Two-wire Slave Interface - TWIS1 PWMA Pulse Width Modulation Controller - PWMA TC0 Timer/Counter - TC0 TC1 Timer/Counter - TC1 ADCIFB ADC Interface - ADCIFB ACIFB Analog Comparator Interface - ACIFB CAT Capacitive Touch Module - CAT GLOC Glue Logic Controller - GLOC AW aWire - AW AT32UC3L016/32/64 34 ...

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... Local Bus Mapped GPIO Registers Register Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) AT32UC3L016/32/64 Local Bus Mode Address Access WRITE 0x40000040 Write-only ...

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... I/O lines 32099F–11/2010 Section 7. on page 41 for power consumption on the various supply pins. Section 6.1.3 for regulator connection figures. Supply Decoupling C C IN3 IN2 C OUT2 AT32UC3L016/32/64 Section 7.9.1 on page 55 VDDIN C IN1 Regulator VDDCORE C OUT1 1.8V 36 ...

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... VDDCORE VDDANA 32099F–11/2010 Figure 6-2 shows the power schematics to be used for 3.3V 3.3V Single Supply Mode + - VDDIN I/O Pins Linear ADC GNDANA AT32UC3L016/32/64 VDDIO GND I/O Pins OSC32K RC32K AST Wake POR33 SM33 CPU, Peripherals, Memories, SCIF, BOD, ...

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... VDDIO = VDDCORE). Figure 6-3. 1.62-1.98V 32099F–11/2010 1.8V Single Supply Mode VDDIN I/O Pins Linear VDDCORE VDDANA GNDANA AT32UC3L016/32/64 Figure 6-3. All I/O lines will be powered by the VDDIO I/O Pins OSC32K RC32K AST Wake POR33 SM33 CPU, Peripherals, ...

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... Supply Mode with 1.8V Regulated I/O Lines 1.98-3.6V + VDDIN - VDDCORE VDDANA GNDANA Section 3.2 on page 9 for description of power supply for each I/O line. AT32UC3L016/32/64 Figure 6-4. This configuration is required in order to VDDIO I/O Pins I/O Pins Linear OSC32K RC32K AST Wake ...

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... The code read from the internal Flash is free to configure the system to use, for example, the DFLL, to divide the frequency of the clock routed to some of the peripherals, and to gate the clocks to unused peripherals. 32099F–11/2010 Table 7-3 on page 42. for the minimum rise rate value. for the frequency for this oscillator. AT32UC3L016/32/64 40 ...

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... Min 1.62 1.62 1.98 1.62 1.62 AT32UC3L016/32/64 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional opera- tion of the device at these or other condi- tions beyond those indicated in the operational sections of this specification is not implied ...

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... GCLK4 clock frequency CAT, ACIFB, GCLK4 pin GCLK5 clock frequency GLOC Table 7-5 are measured values of power consumption under the following condi- = 3.0V VDDIN = 1.62V, supplied by the internal regulator VDDCORE AT32UC3L016/32/64 (1) Rise Rate Min Max Unit 0 2.5 V/µs Slower rise time requires ...

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... Flash enabled in high speed mode • POR33 disabled 32099F–11/2010 • Equivalent to the 3.3V single supply mode • Consumption in 1.8V single supply mode can be estimated by subtracting the regula 1.8V VDDIN VDDCORE • PM, SCIF, AST, FLASHCDW, PBA bridge AT32UC3L016/32/64 (Figure 7-2) - used only when noted 43 ...

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... These numbers are valid for the measured condition only and must not be extrapolated to other frequencies. Figure 7-1. 32099F–11/2010 Measured on (Figure 7-2) (Figure 7-2) Measurement Schematic, Internal Core Supply VDDIN Amp0 VDDIO VDDCORE VDDANA AT32UC3L016/32/64 Consumption Typ 260 165 Amp0 5.3 4.7 600 ...

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... Consumption active is the added current consumption when the module clock is turned on and the module is doing a typical set of operations 32099F–11/2010 Measurement Schematic, External Core Supply VDDIN Amp0 VDDIO VDDCORE VDDANA Table 7-6 are measured values of power consumption under the following = 3.0V VDDIN = 1.62V, supplied by the internal regulator VDDCORE AT32UC3L016/32/64 (Figure 7-1) 45 ...

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... WDT Notes: 32099F–11/2010 Typical Current Consumption by Peripheral (1) 1. Includes the current consumption on VDDANA and ADVREFP. 2. These numbers are valid for the measured condition only and must not be extrapolated to other frequencies. AT32UC3L016/32/64 (2) Typ Consumption Active 14.0 14.9 5.6 6.8 12.4 1.3 3 ...

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... QFN48 package TQFP48 package QFN48 package depending on the supply for the pin. Refer to VDDIN VDDIO (1) Condition PA06 PA02, PB01, RESET PA08, PA09 V = 3.0V VDD V = 1.62V VDD AT32UC3L016/32/64 Min Typ Max 75 100 145 -0.3 0.3*V VDD -0.3 0.3*V VDD 0.7 0.3 VDD VDD ...

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... Refer to VDDIN VDDIO (1) Condition V = 3.0V VDD V = 1.62V VDD V = 3.6V VDD V = 1.98V VDD V = 3.0V 6mA VDD 1.62V 4mA VDD OL AT32UC3L016/32/64 Min Typ Max 0.7 0.3 VDD VDD 0.7 0.3 VDD VDD 0.4 0.4 V -0.4 VDD V -0.4 VDD 45 23 4.7 11.5 4.8 ...

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... TQFP48 package QFN48 package Cbus = 400pF, V > 2.0V VDD Cbus = 400pF, V > 1.62V VDD Cbus = 400pF, V > 2.0V VDD depending on the supply for the pin. Refer to VDDIN VDDIO AT32UC3L016/32/64 Min Typ Max V -0.4 VDD V -0.4 VDD 87 58 2.3 4.3 1.9 3 ...

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... The exact value LEXT is the capacitance of the PCB and PCB Conditions SCIF.OSCCTRL.GAIN = 2 Active mode 0.45MHz, SCIF.OSCCTRL.GAIN = 0 Active mode 10MHz, SCIF.OSCCTRL.GAIN = 2 AT32UC3L016/32/64 Min Typ Max 40 0 7.0 6.7 7-3. The user must choose a crystal oscillator ( ) – ...

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... XOUT C i XIN and the equation above also applies to the 32 KHz oscillator connection. The user can then be found in the crystal datasheet. L Conditions R = 60kOhm 9pF S L (2) (2) 32 768Hz AT32UC3L016/32/64 C LEXT LEXT is within the range given L Min Typ 32 768 (1) 30 000 6 2 0.9 ...

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... REF disabled Accurate lock 8-150kHz, dither REF clk RCSYS/2, SSG disabled Within 90% of final values f = 32kHz, fine lock, SSG disabled REF f = 32kHz, accurate lock, dithering REF clock = RCSYS/2, SSG disabled AT32UC3L016/32/64 Min Typ Max Unit 40 150 MHz 8 150 kHz 0.25 % See Figure 7-4 0 ...

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... These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro- cess technology. These values are not covered by test limits in production. 32099F–11/2010 (1) DFLL Open Loop Frequency variation Tem pera ture Conditions V = 1.8V VDDCORE AT32UC3L016/32/64 1,98V 1,8V 1.62V 60 80 Min Typ Max 88 120 152 1.85 ...

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... Conditions Conditions Calibrated at 85°C gives the device maximum operating frequency depending on the number of flash Read Mode High speed read mode Normal read mode Conditions f = 50MHz CLK_HSB f = 115kHz CLK_HSB AT32UC3L016/32/64 Min Typ Max 0.6 100 Min Typ Max 111.6 115 118.4 ...

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... Condition V >= 1.98V VDDIN I = 0.1mA to 60mA, OUT V > 2.2V VDDIN I = 0.1mA to 60mA, OUT V = 1.98V to 2.2V VDDIN Normal mode Low power mode Normal mode Low power mode Condition 36. AT32UC3L016/32/64 Min Typ Max 100k 10k 15 Min Typ Max 1.98 3.3 3.6 1 Typ Techno. ...

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... Voltage threshold on V POT- t Detection time DET Figure 7-5. V POT+ V POT- 32099F–11/2010 Condition rising VDDCORE falling VDDCORE Time with VDDCORE < V necessary to generate a reset signal POR18 Operating Principles AT32UC3L016/32/64 Min Typ Max Units 1.45 1.58 V 1.2 1.32 POT- 460 µs 56 ...

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... Time with VDDIN < V necessary to generate a reset signal After t RESET POR33 Operating Principles Table 7-25 describe the values of the BODLEVEL in the flash General Purpose BODLEVEL Values Min Typ 1.56 1.65 AT32UC3L016/32/64 Min Typ Max 1.49 1.58 1.3 1.45 POT- 460 15 400 Max ...

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... Startup time STARTUP Note: 1. Calibration value can be read from the SCIF.SM33.CALIB field. This field is updated by the flash fuses after a reset. Refer to SCIF chapter for details. 32099F–11/2010 AT32UC3L016/32/64 Condition Min T = 25°C Time with VDDCORE < BODLEVEL necessary to generate a reset signal Condition ...

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... V = 1.62V to 1.98V VDDIO VDDCORE C ) and a capacitor ( ). In addition the resistance ( ONCHIP ) of the PCB and source must be taken into account when calculating the sample and Figure 7-7 shows the ADC input channel equivalent circuit. AT32UC3L016/32/64 Min Typ Max Units 6 MHz 6 15 µs 11 ...

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... Gain error 32099F–11/2010 ADC Input Positive Input R SOURCE C SOURCE ≥ × ONCHIP ONCHIP OFFCHIP Conditions ADC clock frequency = 6MHz Conditions ADC clock frequency = 6MHz AT32UC3L016/32/64 R ONCHIP C ONCHIP ADCVREFP × OFFCHIP t is defined by the SHTIM field in the SAMPLEHOLD Min Typ Max ...

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... These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro- cess technology. These values are not covered by test limits in production. 32099F–11/2010 (1) Condition Min -0.2 -0.2 = 1.0V, ACREFN = 12MHz, (1) = 12MHz ⎛ ---------------------------------------- ⎝ t CLKACIFB = 3MHz AT32UC3L016/32/64 Min Typ 1 0.5 0 Typ Max V + 0.3 VDDIO V - 0.6 VDDIO 000 000 ⎞ 1 × ...

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... Table 7-34. DICS Characteristics Symbol Parameter R Internal resistor REF k Trim step size 7.9.9.2 Strong Pull-up Pull-down Table 7-35. Strong Pull-up Pull-down Parameter Pull-down resistor Pull-up resistor 32099F–11/2010 AT32UC3L016/32/64 Min Typ Max 120 0.7 Min Typ Max 1 1 Unit kOhm % Unit kOhm 62 ...

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... From wake-up event to the first instruction of an interrupt routine entering the decode stage of the CPU. From wake-up event to the first instruction entering the decode stage of the CPU. (1) Conditions AT32UC3L016/32/64 t Table 7-36. is the period of the CPU clock. If CPU ”Oscillator Characteristics” on page 50 ...

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... USART in SPI Master Mode With (CPOL= 0 and CPHA (CPOL= 1 and CPHA= 0) USPI3 USPI5 (1) Conditions V VDDIO 3.0V to 3.6V, maximum external capacitor = 40pF t ⎛ ⎞ 1 SPCK × – ⎝ ------------------------------------ ⎠ CLKUSART × CLKUSART AT32UC3L016/32/64 USPI1 USPI4 Min Max (2) 30.0+ t SAMPLE from 0 (2) 25 SAMPLE 0 13.6 Units 8 ...

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... T is the SPI slave response time. Please refer to the SPI slave VALID the maximum frequency of the CLK_SPI. Refer to the SPI VALID CLKSPI CPHA= 0) USPI6 USPI7 USPI8 USPI9 USPI10 USPI11 AT32UC3L016/32/64 × CLKSPI , ----------- - ---------------------------- - ( , ) PINMAX SPIn 9 is the maximum frequency of the CLK_SPI. Refer × ...

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... CLKUSART × CLKUSART f = SPCKMAX SPIn is the MOSI setup and hold time, USPI7 + USPI8 or USPI10 + USPI11 depending f is the maximum frequency of the CLK_SPI. Refer to the SPI CLKSPI AT32UC3L016/32/64 USPI13 USPI15 Min ( SAMPLE CLK_USART 0 from ( SAMPLE CLK_USART 0 25.0 0 25.0 0 × ...

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... MISO MOSI 32099F–11/2010 f CLKSPI f MIN ---------------------------- - SPCKMAX SPIn is the MISO delay, USPI6 or USPI9 depending on CPOL and NCPHA. is the maximum frequency of the SPI pins. Please refer to the I/O Pin Characteris- SPI0 SPI2 SPI3 SPI5 AT32UC3L016/32/64 × ------------------------------------ ) PINMAX SPIn SETUP T SETUP SPI1 SPI4 ...

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... MOSI delay, SPI2 or SPI5 depending on CPOL and NCPHA. f SPCKMAX SPIn is the MISO setup and hold time, SPI0 + SPI1 or SPI3 + SPI4 depending the SPI slave response time. Please refer to the SPI slave VALID t . VALID SPI6 SPI7 SPI8 AT32UC3L016/32/64 Min 28 )/2 CLK_SPI from 0 22 )/2 CLK_SPI 0 1 MIN f = ...

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... Maximum SPI Frequency, Slave Input Mode 32099F–11/2010 SPI9 SPI10 SPI11 SPI Slave Mode NPCS Timing SPI12 SPI14 (1) Conditions V from VDDIO 3.0V to 3.6V, maximum external capacitor = 40pF AT32UC3L016/32/64 SPI13 SPI15 Min Max Units 79.9 49.4 4.1 80.8 48.8 ns 3.5 4.9 2.7 3.8 3.2 69 ...

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... Minimum Mode Requirement (1) Standard - (1) Fast 20 + 0.1C Standard - Fast 20 + 0.1C Standard 4 Fast 0.6 Standard 4.7 Fast 0.6 Standard 4.0 Fast 0.6 Standard (2) 0.3 Fast AT32UC3L016/32/64 1 MIN ----------- - ) CLKSPI SPIn ------------------------------------ ) PINMAX SPIn t + SETUP t . SETUP ) are met by the device without requiring user inter HD-STA SU-STA ...

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... Fast 0.6 Standard - Fast > 100 kHz f 100 kHz ; fast mode: TWCK = period of TWI internal prescaled clock (see chapters on TWIM and TWIS) has only to be met if the device does not stretch the LOW period (t HD;DAT AT32UC3L016/32/64 Maximum Device Requirement 2t - clkpb t - clkpb 4t - clkpb t ...

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... These values are not covered by test limits in production. 32099F–11/2010 JTAG2 TCK JTAG0 JTAG3 TDO JTAG5 JTAG6 JTAG7 Conditions V from VDDIO 3.0V to 3.6V, maximum external capacitor = 40pF AT32UC3L016/32/64 JTAG1 JTAG4 JTAG8 JTAG9 JTAG10 Min Max 23.2 8.8 32.0 3.9 0.6 4.5 23.2 0 5.0 8.7 17.7 ...

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... × θ ( θ HEATSINK JC 8-1. = cooling device thermal resistance (°C/W), provided in the device datasheet. AT32UC3L016/32/64 Condition Package Still Air TQFP48 TQFP48 Still Air QFN48 QFN48 Still Air TLLGA48 TLLGA48 , in °C can be obtained from the following: J Typ Unit 63.2 °C/W 21.8 28.3 ° ...

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... Package Drawings Figure 8-1. TQFP-48 Package Drawing Table 8-2. Device and Package Maximum Weight 140 Table 8-3. Package Characteristics Moisture Sensitivity Level Table 8-4. Package Reference JEDEC Drawing Reference JESD97 Classification 32099F–11/2010 AT32UC3L016/32/64 mg MSL3 MS-026 E3 74 ...

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... Figure 8-2. QFN-48 Package Drawing Note: The exposed pad is not connected to anything. Table 8-5. Device and Package Maximum Weight 140 Table 8-6. Package Characteristics Moisture Sensitivity Level Table 8-7. Package Reference JEDEC Drawing Reference JESD97 Classification 32099F–11/2010 AT32UC3L016/32/64 mg MSL3 M0-220 E3 75 ...

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... Figure 8-3. TLLGA-48 Package Drawing Table 8-8. Device and Package Maximum Weight 39.3 Table 8-9. Package Characteristics Moisture Sensitivity Level Table 8-10. Package Reference JEDEC Drawing Reference JESD97 Classification 32099F–11/2010 AT32UC3L016/32/64 mg MSL3 M0-220 E4 76 ...

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... Time within 5°C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25°C to Peak Temperature A maximum of three reflow passes is allowed per component. 32099F–11/2010 gives the recommended soldering profile from J-STD-20. Soldering Profile AT32UC3L016/32/64 Green Package 3°C/s max 150-200°C 60-150 260°C 6°C/s max ...

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... Ordering Code AT32UC3L064-AUTES AT32UC3L064-AUT AT32UC3L064-AUR AT32UC3L064-ZAUES AT32UC3L064 AT32UC3L064-ZAUT AT32UC3L064-ZAUR AT32UC3L064-D3HES AT32UC3L064-D3HT AT32UC3L064-D3HR AT32UC3L032-AUT AT32UC3L032-AUR AT32UC3L032-ZAUT AT32UC3L032 AT32UC3L032-ZAUR AT32UC3L032-D3HT AT32UC3L032-D3HR AT32UC3L016-AUT AT32UC3L016-AUR AT32UC3L016-ZAUT AT32UC3L016 AT32UC3L016-ZAUR AT32UC3L016-D3HT AT32UC3L016-D3HR 32099F–11/2010 Carrier Type Package Package Type ES Tray TQFP 48 Tape & Reel JESD97 Classification E3 ES Tray QFN 48 Tape & ...

Page 79

... While turning off the CFD, the CFD bit in the Status Register (SR) can be set. This will change the main clock source to RCSYS. Fix/Workaround Solution 1: Enable CFD interrupt. If CFD interrupt is issues after turning off the CFD, switch back to original main clock source. 32099F–11/2010 AT32UC3L016/32/64 79 ...

Page 80

... Watchdog reset immediately. If the WDT counter is not cleared at all, the time before the reset will be twice as long as needed. 10.1.7 GPIO 1. Clearing GPIO interrupt may fail Writing a one to the GPIO.IFRC register to clear the interrupt will be ignored if interrupt is enabled for the corresponding port. 32099F–11/2010 AT32UC3L016/32/64 80 ...

Page 81

... SR.IDLE to go high and then immediately disables the TWIM by writing a one to CR.MDIS. Disabling the TWIM causes the TWCK and TWD pins to go high immediately, so the STOP condition will not be transmitted correctly. Fix/Workaround 32099F–11/2010 AT32UC3L016/32/64 81 ...

Page 82

... CAT module for up to n-1 PB clocks at the end of burst charging sequence, this will greatly reduce the amount of charge that is prematurely lost from the sense capacitors, because the discharge time constant will now be approximately 32099F–11/2010 AT32UC3L016/32/64 82 ...

Page 83

... OSC0 is disabled Solution 2: Pull down or up XIN0 and XOUT0 with 1MOhm resistor. 10.1.15 I/O Pins 1. PA17 has low ESD tolerance PA17 only tolerates 500V ESD pulses (Human Body Model). Fix/Workaround Care must be taken during manufacturing and PCB design. 32099F–11/2010 AT32UC3L016/32/64 83 ...

Page 84

... Power-on Reset (POR), and not as a SLEEP reset, in the Reset Cause register (RCAUSE). Fix/Workaround None. 3. Disabling POR33 may generate spurious resets Depending on operating conditions, POR33 may generate a spurious reset in one of the fol- lowing cases: - When POR33 is disabled from the user interface. - When SM33 supply monitor is enabled. 32099F–11/2010 AT32UC3L016/32/64 84 ...

Page 85

... If a reset occurs and the AST is enabled, the SR.ALARM0, SR.PER0, and SR.OVF bits may be set. Fix/Workaround If the part is reset and the AST is used, clear all bits in the Status Register (SR) before enter- ing sleep mode. 2. AST wake signal is released one AST clock cycle after the BUSY bit is cleared 32099F–11/2010 AT32UC3L016/32/64 85 ...

Page 86

... Fix/Workaround Disable mode fault detection by writing a one to MR.MODFDIS. 4. Disabling SPI has no effect on the SR.TDRE bit Disabling SPI has no effect on SR.TDRE whereas the write data command is filtered when SPI is disabled. This means that as soon as the SPI is disabled it becomes impossible to 32099F–11/2010 AT32UC3L016/32/64 86 ...

Page 87

... PWMA clock period. Fix/Workaround Ensure that duty cycle writes from the user interface are not performed in a PWMA clock period when an incoming peripheral event is expected. 10.2.11 CAT 1. CAT asynchronous wake will be delayed by one AST peripheral event period 32099F–11/2010 AT32UC3L016/32/64 87 ...

Page 88

... Fix/Workaround Do not write values larger than 0x1F to ACR.STARTUP. 2. ADCIFB DMA transfers does not work with divided PBA clock DMA requests from the ADCIFB will not be performed when the PBA clock is slower than the HSB clock. Fix/Workaround 32099F–11/2010 AT32UC3L016/32/64 88 ...

Page 89

... Make a DTLB Protection (Write) exception handler which permits the interrupt request to be handled in privileged mode. 2. Hardware breakpoints may corrupt MAC results Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC instruction. Fix/Workaround Place breakpoints on earlier or later instructions. 32099F–11/2010 AT32UC3L016/32/64 89 ...

Page 90

... VERSION register reads 0x100 The VERSION register reads 0x100 instead of 0x102. Fix/Workaround None. 10.4.3 HMATRIX 1. In the PRAS and PRBS registers, the MxPR fields are only two bits 32099F–11/2010 AT32UC3L016/32/64 90 ...

Page 91

... This will result in a significantly higher power consump- tion during the sleep mode. Fix/Workaround Before going to sleep modes where RCSYS is stopped, make sure the division factor between the CPU/HSB and PBx frequencies is less than or equal to 4. 32099F–11/2010 AT32UC3L016/32/64 91 ...

Page 92

... It is not possible to mask the request clock requests using PPCR. Fix/Workaround None. 9. Clock failure detector (CFD) does not work The clock failure detector does not work. Fix/Workaround None. 10. Instability when exiting sleep walking If all the following operating conditions are true, exiting sleep walking might lead to instability: 32099F–11/2010 AT32UC3L016/32/64 92 ...

Page 93

... Write the desired value added by two to the DFLL0CONF.FINE field. 4. BODVERSION register reads 0x100 The BODVERSION register reads 0x100 instead of 0x101. Fix/Workaround None. 5. BRIFA is non-functional BRIFA is non-functional. Fix/Workaround None. 6. VREGCR.DEEPMODEDISABLE bit is not readable VREGCR.DEEPMODEDISABLE bit is not readable. Fix/Workaround None. 7. DFLL step size should lower below 30 MHz 32099F–11/2010 AT32UC3L016/32/64 93 ...

Page 94

... None. 14. RCCRVERSION register reads 0x100 The RCCRVERSION register reads 0x100 instead of 0x101. Fix/Workaround None. 15. OSC32VERSION register reads 0x100 The OSC32VERSION register reads 0x100 instead of 0x101. Fix/Workaround None. 16. VREGVERSION register reads 0x100 The VREGVERSION register reads 0x100 instead of 0x101. 32099F–11/2010 AT32UC3L016/32/64 94 ...

Page 95

... WDT. Fix/Workaround Check SR.WINDOW immediately after clearing the WDT. If set then clear the WDT once more. 2. VERSION register reads 0x400 The VERSION register reads 0x400 instead of 0x402. 32099F–11/2010 AT32UC3L016/32/64 TBAN CLK_WDT cycles after entering the window ...

Page 96

... In the interrupt handler code, write a one to the RTSDIS bit in the USART Control Register (CR). This will drive the RTS output high. After the next DMA trans- fer is started and a receive buffer is available, write a one to the RTSEN bit in the USART CR so that RTS will be driven low. 32099F–11/2010 AT32UC3L016/32/64 96 ...

Page 97

... TWIS Version Register (VR) reads zero instead of 0x112. Fix/Workaround None. 3. TWIS CR.STREN does not work in deep sleep modes When the device is in Stop, DeepStop, or Static mode, address reception will not wake the device if both CR.SOAM and CR.STREN are one. 32099F–11/2010 AT32UC3L016/32/64 97 ...

Page 98

... Enable the TWIM first and then enable the TWD and TWCK peripheral pins in the GPIO controller necessary to disable the TWIM, first disable the TWD and TWCK peripheral pins in the GPIO controller and then disable the TWIM. 2. TWIM SMBAL polarity is wrong The SMBAL signal in the TWIM is active high instead of active low. Fix/Workaround 32099F–11/2010 AT32UC3L016/32/64 98 ...

Page 99

... Ensure that duty cycle writes from the user interface are not performed in a PWMA clock period when an incoming peripheral event is expected. 10.4. When the main clock is RCSYS, TIMER_CLOCK5 is equal to CLK_PBA When the main clock is generated from RCSYS, TIMER_CLOCK5 is equal to CLK_PBA and not CLK_PBA/128. Fix/Workaround None. 32099F–11/2010 AT32UC3L016/32/64 99 ...

Page 100

... Fix/Workaround None. 2. Generic clock sources in sleep modes The ACIFB should not use RC32K or CLK_1K as generic clock source if the chip uses sleep modes. Fix/Workaround None. 3. VERSION register reads 0x200 The VERSION register reads 0x200 instead of 0x212. Fix/Workaround None. 32099F–11/2010 AT32UC3L016/32/64 100 ...

Page 101

... AST event. For example, if the AST is gen- erating peripheral events to the CAT every 50 milliseconds, and the CAT detects a touch at t=9200 milliseconds, the asynchronous wake will occur at t=9250 milliseconds. Fix/Workaround None. 32099F–11/2010 AT32UC3L016/32/64 101 ...

Page 102

... Reset the aWire by keeping the RESET_N line low for 100ms. 4. aWire enable does not work in Static mode aWire enable does not work in Static mode. Fix/Workaround None. 5. VERSION register reads 0x200 The VERSION register reads 0x200 instead of 0x210. Fix/Workaround None. 32099F–11/2010 AT32UC3L016/32/64 102 ...

Page 103

... Pins PA02, PB01, PB04, PB05, and RESET_N have half of the specified pull-up strength. Fix/Workaround None. 4. OCD MCKO and MDO[3] are swapped in the AUX1 mapping When using the OCD AUX1 mapping of trace signals MDO[3] is located on pin PB05 and MCKO is located on PB01. 32099F–11/2010 AT32UC3L016/32/64 103 ...

Page 104

... Swap pins PB01 and PB05 if using OCD AUX1. 5. The JTAG is enabled at power up The JTAG function on pins PA00, PA01, PA02, and PA03, are enabled after startup. Normal I/O module functionality is not possible on these pins. Fix/Workaround Add a 10kOhm pullup on the reset line. 32099F–11/2010 AT32UC3L016/32/64 104 ...

Page 105

... TWIS: SCR is Write-only. Improved explanation of slave transmitter mode. Updated data transfer diagrams. Electrical Characteristics: Added more values. Added notes on simulated and characterized values. Added pin capacitance, rise, and fall times. Added timing characteristics. Removed all TBDs. Added ADC analog input characteristics. Symbol cleanup. Errata: Updated errata list. AT32UC3L016/32/64 105 ...

Page 106

... Ordering Information: Ordering code for TQFP ES changed from AT32UC3L064-AUES to AT32UC3L064-AUTES. TLLGA48 Tray option added. Features and Description: Added QTouch library support. USART: Description of unimplemented features removed. Electrical Characteristics: Power Consumption numbers updated. Flash timing numbers added. Package and Pinout: Added pinout figure for TLLGA48 package. ...

Page 107

... CONF.EVENN bits are swapped. CAT: Matrix size not Electrical Characteristics: General update. Mechanical Characteristics: Added numbers for package drawings. Mechanical Characteristics: In the TQFP-48 package drawing the Lead Coplanarity is 0.102mm, not 0.080mm. Ordering Information: Ordering code for TLLGA-48 package updated. Initial revision. AT32UC3L016/32/64 107 ...

Page 108

... Physical Memory Map .....................................................................................32 5.3 Peripheral Address Map ..................................................................................33 5.4 CPU Local Bus Mapping .................................................................................34 6.1 Supply Considerations .....................................................................................36 6.2 Startup Considerations ....................................................................................40 7.1 Disclaimer ........................................................................................................41 7.2 Absolute Maximum Ratings* ...........................................................................41 7.3 Supply Characteristics .....................................................................................41 7.4 Maximum Clock Frequencies ..........................................................................42 7.5 Power Consumption ........................................................................................42 7.6 I/O Pin Characteristics .....................................................................................47 7.7 Oscillator Characteristics .................................................................................50 AT32UC3L016/32/64 i ...

Page 109

... Soldering Profile ..............................................................................................77 10.1 Rev. E ..............................................................................................................79 10.2 Rev. D ..............................................................................................................84 10.3 Rev. C ..............................................................................................................89 10.4 Rev. B ..............................................................................................................89 11.1 Rev. F- 11/2010 .............................................................................................105 11.2 Rev. E- 10/2010 .............................................................................................105 11.3 Rev 06/2010 ...........................................................................................106 11.4 Rev 06/2010 ...........................................................................................106 11.5 Rev 05/2010 ............................................................................................106 11.6 Rev. A – 06/2009 ...........................................................................................107 AT32UC3L016/32/64 ii ...

Page 110

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...