DSPIC33FJ128GP802-E/MM Microchip Technology, DSPIC33FJ128GP802-E/MM Datasheet - Page 216

IC, DSC, 16BIT, 128KB 40MHZ, 3.6V, QFN28

DSPIC33FJ128GP802-E/MM

Manufacturer Part Number
DSPIC33FJ128GP802-E/MM
Description
IC, DSC, 16BIT, 128KB 40MHZ, 3.6V, QFN28
Manufacturer
Microchip Technology
Series
DsPIC33Fr

Specifications of DSPIC33FJ128GP802-E/MM

Core Frequency
40MHz
Core Supply Voltage
3.6V
No. Of I/o's
21
Flash Memory Size
128KB
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-40°C To +125°C
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b, D/A 4x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-QFN
Rohs Compliant
Yes
Package
28QFN-S EP
Device Core
dsPIC
Family Name
dSPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
16 Bit
Number Of Programmable I/os
21
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
10-chx10-bit|10-chx12-bit
On-chip Dac
2-chx16-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 18-1:
DS70292E-page 216
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9-8
bit 7
bit 6
bit 5
Note 1:
UARTEN
R/W-0 HC
R/W-0
WAKE
2:
(1)
Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for
information on enabling the UART module for receive or transmit operation.
This feature is only available for the 16x BRG mode (BRGH = 0).
UARTEN: UARTx Enable bit
1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>
0 = UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption
Unimplemented: Read as ‘0’
USIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
IREN: IrDA
1 = IrDA
0 = IrDA
RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin in Simplex mode
0 = UxRTS pin in Flow Control mode
Unimplemented: Read as ‘0’
UEN<1:0>: UARTx Enable bits
11 = UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin controlled by port latches
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by port latches
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLK pins controlled by
WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit
1 = UARTx continues to sample the UxRX pin; interrupt generated on falling edge; bit cleared
0 = No wake-up enabled
LPBACK: UARTx Loopback Mode Select bit
1 = Enable Loopback mode
0 = Loopback mode is disabled
ABAUD: Auto-Baud Enable bit
1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h)
0 = Baud rate measurement disabled or completed
LPBACK
R/W-0
minimal
in hardware on following rising edge
before other data; cleared in hardware upon completion
U-0
port latches
UxMODE: UART
®
®
encoder and decoder enabled
encoder and decoder disabled
®
Encoder and Decoder Enable bit
HC = Hardware cleared
W = Writable bit
‘1’ = Bit is set
R/W-0 HC
ABAUD
USIDL
R/W-0
x
MODE REGISTER
(1)
URXINV
IREN
R/W-0
R/W-0
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
RTSMD
(2)
BRGH
R/W-0
R/W-0
R/W-0
U-0
PDSEL<1:0>
© 2011 Microchip Technology Inc.
x = Bit is unknown
R/W-0
R/W-0
UEN<1:0>
STSEL
R/W-0
R/W-0
bit 8
bit 0

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