ADSP-BF538BBCZ-4F4 Analog Devices Inc, ADSP-BF538BBCZ-4F4 Datasheet
ADSP-BF538BBCZ-4F4
Specifications of ADSP-BF538BBCZ-4F4
Related parts for ADSP-BF538BBCZ-4F4
ADSP-BF538BBCZ-4F4 Summary of contents
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... MEMORY 148K bytes of on-chip memory 16K bytes of instruction SRAM/cache 64K bytes of instruction SRAM 32K bytes of data SRAM 32K bytes of data SRAM/cache 4K bytes of scratchpad SRAM 512K 16-bit or 256K 16-bit flash memory (ADSP-BF538F only) PERIPHERAL ACCESS BUS TWI0-1 CAN 2.0B GPIO PORT C GPIO ...
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... REVISION HISTORY 10/08—Rev Rev. B Corrected document errata associated with Pin Descriptions .................................................... 19 Corrected document errata associated with I trical Characteristics ............................................... 25 Removed the Power Dissipation section. See Estimating Power for the ADSP-BF538/BF539 Blackfin Processors (EE-298) and Table 15, Table 16, and Table 17 ................................ Revised SPI master timing specifications and diagram. ...
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... I/O pins ADSP-BF538/ADSP-BF538F PROCESSOR 3 PERIPHERALS 2 The ADSP-BF538/ADSP-BF538F processors contain a rich set 1 of peripherals connected to the core via several high bandwidth buses, providing flexibility in system configuration as well as 1 excellent overall system performance (see the block diagram 16K bytes on Page 1) ...
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... ADSP-BF538/ADSP-BF538F BLACKFIN PROCESSOR CORE As shown in Figure 2 on Page 4, the Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The compu- tation units process 8-bit, 16-bit, or 32-bit data from the register file. ...
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... C/C++ compiler, resulting in fast and efficient software implementations. MEMORY ARCHITECTURE The ADSP-BF538/ADSP-BF538F processors view memory as a single unified 4G byte address space, using 32-bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space ...
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... Spansion S29AL004D known good die flash mem- † ory . The ADSP-BF538F8 contains an 8M bit (512K 16-bit) bottom boot sector Spansion S29AL008D known good die flash memory. The following features are also included: • access times as fast (EBIU registers must be set appropriately) • ...
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... The system interrupt controllers (SIC) provides the mapping and routing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the CEC. Although the ADSP-BF538/ADSP-BF538F processors provide a default mapping, programs can alter the mappings and priorities of interrupt events by writing the appropriate val- ues into the interrupt assignment registers (SIC_IARx) ...
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... DMA CONTROLLERS The ADSP-BF538/ADSP-BF538F processors have two, inde- pendent DMA controllers that support automated data transfers with minimal overhead for the processor core. DMA transfers can occur between the processor internal memories and any of its DMA capable peripherals ...
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... The timer is clocked by the system clock (SCLK maximum frequency of f SCLK TIMERS There are four general-purpose programmable timer units in the ADSP-BF538/ADSP-BF538F processors. Three timers have an external pin that can be configured either as a pulse-width Rev Page October 2008 ADSP-BF538/ADSP-BF538F 5. RTXO ...
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... The serial clock line synchronizes the shifting and sam- pling of data on the two serial data lines. 2-WIRE INTERFACE The ADSP-BF538/ADSP-BF538F processors have two 2-wire interface (TWI) modules that are compatible with the Philips Inter-IC bus standard. The TWI modules offer the capabilities of simultaneous master and slave operation, support for 7-bit addressing and multimedia data arbitration ...
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... The capabilities of the UARTs are further extended with sup- port for the Infrared Data Association (IrDA Physical Layer Link Specification (SIR) protocol. GENERAL-PURPOSE PORTS The ADSP-BF538/ADSP-BF538F processors have gen- eral-purpose I/O pins that are multiplexed with other peripherals. They are arranged into Ports and F as shown in Table 4 ...
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... PPI_CONTROL register. Frame Capture Mode Frame capture mode allows the video source(s) to act as a slave (e.g., for frame capture). The ADSP-BF538/ADSP-BF538F pro- cessors control when to read from the video source(s). PPI_FS1 is an HSYNC output and PPI_FS2 is a VSYNC output. Output Mode Output mode is used for transmitting video or other data with up to three output frame syncs ...
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... DYNAMIC POWER MANAGEMENT The ADSP-BF538/ADSP-BF538F processors provide four oper- ating modes, each with a different performance/power profile. In addition, dynamic power management provides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation ...
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... Analog Devices website (www.analog.com)—use site search on “EE-228”. 100% CLOCK SIGNALS The ADSP-BF538/ADSP-BF538F processors can be clocked by an external crystal, a sine wave input buffered, shaped clock derived from an external clock oscillator external clock is used, it should be a TTL-compatible signal ...
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... Table 8. Core Clock Ratios Signal Name CSEL1– BOOTING MODES The ADSP-BF538/ADSP-BF538F processors have three mecha- nisms (listed in instruction memory after a reset. A fourth mode is provided to ON-THE-FLY execute from external memory, bypassing the boot sequence CCLK Table 9. Booting Modes BMODE1–0 Description ...
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... Boot from 8-bit or 16-bit external flash memory – The 8-bit flash boot routine located in boot ROM memory space is set up using asynchronous memory bank 0. For ADSP-BF538F processors, the on-chip flash is booted if FCE is connected to AMS0. All configuration settings are set for the slowest device possible (3-cycle hold time; ...
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... File (LDF), allowing the developer to move between the graphi- cal and textual environments. Analog Devices emulators use the IEEE 1149.1 JTAG Test Access Port of the ADSP-BF538/ADSP-BF538F processors to monitor and control the target board processor during emula- tion. The emulator provides full speed emulation, allowing inspection and modification of memory, registers, and proces- sor stacks ...
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... This document is updated regularly to keep pace with improvements to emulator support. RELATED DOCUMENTS The following publications that describe the ADSP-BF538/ ADSP-BF538F processors (and related processors) can be ordered from any Analog Devices sales office or accessed elec- tronically on our website: • ...
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... Hardware Ready Control (This pin should always be pulled low when not used.) Output Enable Read Enable Write Enable Flash Enable (This pin is internally connected to GND on the ADSP-BF538.) Flash Reset (This pin is internally connected to GND on the ADSP-BF538.) Row Address Strobe Column Address Strobe Write Enable Clock Enable Clock Output ...
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... ADSP-BF538/ADSP-BF538F Table 10. Pin Descriptions (Continued) Pin Name I/O SDA0 I SCL0 I SDA1 I SCL1 I Serial Port0 RSCLK0 I/O RFS0 I/O DR0PRI I DR0SEC I TSCLK0 I/O TFS0 I/O DT0PRI O DT0SEC O Serial Port1 RSCLK1 I/O RFS1 I/O DR1PRI I DR1SEC I TSCLK1 I/O TFS1 I/O DT1PRI O DT1SEC O SPI0 Port ...
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... GPIO/SPI0 Slave Select Enable 1/Timer Alternate Clock Input GPIO/SPI0 Slave Select Enable 2 GPIO/PPI Frame Sync 3/SPI0 Slave Select Enable 3 GPIO/PPI15/SPI0 Slave Select Enable 4 GPIO/PPI14/SPI0 Slave Select Enable 5 GPIO/PPI13/SPI0 Slave Select Enable 6 GPIO/PPI12/SPI0 Slave Select Enable 7 Rev Page October 2008 ADSP-BF538/ADSP-BF538F Driver Type ...
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... ADSP-BF538/ADSP-BF538F Table 10. Pin Descriptions (Continued) Pin Name I/O PF8/PPI11 I/O PF9/PPI10 I/O PF10/PPI9 I/O PF11/PPI8 I/O PF12/PPI7 I/O PF13/PPI6 I/O PF14/PPI5 I/O PF15/PPI4 I/O Real-Time Clock RTXI I RTXO O JTAG Port TCK I TDO O TDI I TMS I TRST I EMU O Clock CLKIN I XTAL O Mode Controls ...
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... Parameter value applies to the CLKIN input pin. 6 Parameter value applies to all input and bidirectional pins. The following tables describe the voltage/frequency require- ments for the ADSP-BF538/ADSP-BF538F processor clocks. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to Table 11. Core Clock (CCLK) Requirements - 400 MHz Models Parameter ...
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... ADSP-BF538/ADSP-BF538F Table 12. Core Clock (CCLK) Requirements - 533 MHz Models Parameter f Core Clock Frequency (V = 1.2 V Minimum) CCLK DDINT f Core Clock Frequency (V = 1.14 V Minimum) CCLK DDINT f Core Clock Frequency (V = 1.045 V Minimum) CCLK DDINT f Core Clock Frequency (V = 0.95 V Minimum) CCLK DDINT f Core Clock Frequency ( ...
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... Applies to three-statable pins. 6 Applies to all signal pins. 7 Guaranteed, but not tested. 8 See the ADSP-BF538/538F Blackfin Processor Hardware Reference Manual for definitions of sleep, deep sleep, and hibernate operating modes. 9 See Table 16 for the list of I power vectors covered by various Activity Scaling Factors (ASF). ...
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... ADSP-BF538/ADSP-BF538F System designers should refer to Estimating Power for the ADSP-BF538/BF539 Blackfin Processors (EE-298), which pro- vides detailed information for optimizing designs for lowest power. All topics discussed in this section are described in detail in EE-298. Total power dissipation has two components: 1. Static, including leakage current 2 ...
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... N/A N/A N/A 145.0 151.8 N/A N/A N/A N/A 159.9 N/A N/A N/A N/A N/A Rev Page October 2008 ADSP-BF538/ADSP-BF538F ) 1.20 V 1.25 V 1.30 V 1.32 V 25.4 27.1 29.1 29.7 41.7 44.3 46.4 47.6 74.3 76.2 82.2 83.4 89.8 94.2 99 ...
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... Rev Page October 2008 Figure 9 and Table 19 provides Ordering Guide on Page 58. a ADSP-BF538Fx tppZccc vvvvvv.x n.n #yyww country_of_origin B Figure 9. Product Information on Package Field Description On-Chip Flash Option bit) Temperature Range Package Type RoHS Compliant Part See Ordering Guide ...
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... Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted, assuming stable power supplies and CLKIN (not including startup time of external clock oscillator). t CKIN CLKIN t CKINL RESET 4 t CKINH t WRST Figure 10. Clock and Reset Timing Rev Page October 2008 ADSP-BF538/ADSP-BF538F Min Max 20.0 100.0 8.0 8 CKIN Unit ...
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... ADSP-BF538/ADSP-BF538F Asynchronous Memory Read Cycle Timing Table 21 and Table 22 on Page 31 and Figure 11 on Page 31 describe asynchronous memory read cycle opera- tions for synchronous and for asynchronous ARDY. Table 21. Asynchronous Memory Read Cycle Timing with Synchronous ARDY Parameter Timing Requirements t DATA15–0 Setup Before CLKOUT ...
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... ADDR19–1 AOE ARE t DANR ARDY DATA15–0 Figure 12. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY PROGRAMMED READ ACCESS ACCESS EXTENDED 4 CYCLES BE, ADDRESS t DO Rev Page October 2008 ADSP-BF538/ADSP-BF538F Min Max Unit 2 – SCLK 0.0 ns 6.0 ns 0.8 ns HOLD ...
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... ADSP-BF538/ADSP-BF538F Asynchronous Memory Write Cycle Timing Table 23 and Table 24 on Page 33 and Figure 13 on Page 33 describe asynchronous memory write cycle opera- tions for synchronous and for asynchronous ARDY. Table 23. Asynchronous Memory Write Cycle Timing with Synchronous ARDY Parameter Timing Requirements t ARDY Setup Before the Falling Edge of CLKOUT ...
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... ARDY t ENDAT DATA15–0 WRITE DATA Figure 14. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY ACCESS PROGRAMMED WRITE EXTENDED ACCESS 2 CYCLES BE, ADDRESS t HO Rev Page October 2008 ADSP-BF538/ADSP-BF538F Min Max ( – 0.0 6.0 1.0 6.0 0.8 HOLD 1 CYCLE HAA t DDAT Unit ...
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... ADSP-BF538/ADSP-BF538F SDRAM Interface Timing Table 25. SDRAM Interface Timing Parameter Timing Requirements t DATA Setup Before CLKOUT SSDAT t DATA Hold After CLKOUT HSDAT Switching Characteristics t CLKOUT Period SCLK t CLKOUT Width High SCLKH t CLKOUT Width Low SCLKL t Command, ADDR, Data Delay After CLKOUT DCAD ...
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... CLKOUT High to BGH Deasserted Hold Time EBH CLKOUT BR AMSx ADDR19-1 ABE1-0 AWE ARE BG BGH Figure 16. External Port Bus Request and Grant Cycle Timing with Synchronous BR and Figure Rev Page October 2008 ADSP-BF538/ADSP-BF538F Min Max 4.6 1.0 4.5 4.5 4.0 4.0 3.6 3 ...
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... ADSP-BF538/ADSP-BF538F Table 27. External Port Bus Request and Grant Cycle Timing with Asynchronous BR Parameter Timing Requirement t BR Pulse Width WBR Switching Characteristics t CLKOUT Low to AMSx, Address, and ARE/AWE Disable SD t CLKOUT Low to AMSx, Address, and ARE/AWE Enable SE t CLKOUT High to BG High Setup ...
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... Figure 21 FRAME DATA0 SYNC IS IS DRIVEN SAMPLED OUT t DFSPE t HOFSPE t t SDRPE HDRPE Figure 18. PPI GP Rx Mode with Internal Frame Sync Timing Rev Page October 2008 ADSP-BF538/ADSP-BF538F Min Max 6.0 15.0 5.0 1.0 2.0 4.0 10.0 0.0 10.0 0.0 Unit ...
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... ADSP-BF538/ADSP-BF538F DATA0 IS SAMPLED PPI_CLK POLC = 0 PPI_CLK POLC = 1 POLS = 1 PPI_FS1 POLS = 0 POLS = 1 PPI_FS2 POLS = 0 t SDRPE PPI_DATA PPI_CLK POLC = 0 PPI_CLK POLC = 1 POLS = 1 PPI_FS1 POLS = 0 POLS = 1 PPI_FS2 POLS = 0 PPI_DATA FRAME SYNC IS SAMPLED FOR DATA1 IS DATA0 SAMPLED t HFSPE t SFSPE t HDRPE Figure 19. PPI GP Rx Mode with External Frame Sync Timing ...
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... FRAME SYNC IS REFERENCED TO THIS CLOCK EDGE PPI_CLK POLC = 0 PPI_CLK POLC = 1 t DFSPE t HOFSPE POLS = 1 PPI_FS1 POLS = 0 POLS = 1 PPI_FS2 POLS = 0 PPI_DATA DATA0 IS DRIVEN OUT t DDTPE t HDTPE DATA0 Figure 21. PPI GP Tx Mode with Internal Frame Sync Timing Rev Page October 2008 ADSP-BF538/ADSP-BF538F ...
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... ADSP-BF538/ADSP-BF538F Serial Port Timing Table 29 through Table 32 on Page 41 and through Figure 23 on Page 42 describe serial port operations. Table 29. Serial Ports—External Clock Parameter Timing Requirements t TFSx/RFSx Setup Before TSCLKx/RSCLKx (Externally Generated TFSx/RFSx) SFSE t TFSx/RFSx Hold After TSCLKx/RSCLKx (Externally Generated TFSx/RFSx) ...
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... HFSI HOFSE RFSx t HDRI DRx DATA TRANSMIT—EXTERNAL CLOCK SAMPLE EDGE TSCLKx t t HFSI HOFSE TFSx DTx Figure 22. Serial Ports Rev Page October 2008 ADSP-BF538/ADSP-BF538F Min Max 1, 2 10.0 0 and t apply. DDTLFSE DTENLFS DRIVE SAMPLE EDGE EDGE t SCLKEW t DFSE t SFSE ...
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... ADSP-BF538/ADSP-BF538F EXTERNAL RFSx IN MULTICHANNEL MODE WITH MFD = 0 RSCLKx RFSx DTx LATE EXTERNAL TFSx TSCLKx TFSx DTx DRIVE SAMPLE DRIVE t t SFSE/I HOFSE/I t DDTTE/I t DTENLFS t DTENE/I 1ST BIT t DDTLFSE DRIVE SAMPLE DRIVE t HOFSE/I t SFSE/I t DDTTE/I t DTENLFS t DTENE/I 1ST BIT t DDTLFSE Figure 23. External Late Frame Sync Rev ...
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... SPICHM SPICLM t t SPICLM SPICHM t t HDSPIDM DDSPIDM MSB MSB VALID t HDSPIDM MSB t HSPIDM Figure 24. Serial Peripheral Interface (SPI) Ports—Master Timing Rev Page October 2008 ADSP-BF538/ADSP-BF538F Min Max 9.0 –1.5 2t SCLK 2t –1.5 SCLK 2t –1.5 SCLK 4t SCLK 2t SCLK 2t SCLK 5 –1.0 t ...
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... ADSP-BF538/ADSP-BF538F Serial Peripheral Interface Ports—Slave Timing Table 34 and Figure 25 describe SPI port’s slave operations. Table 34. Serial Peripheral Interface (SPI) Ports—Slave Timing Parameter Timing Requirements t Serial Clock High Period SPICHS t Serial Clock Low Period SPICLS t Serial Clock Period SPICLK ...
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... GP Port Pin Input Pulse Width WFI Switching Characteristic t GP Port Pin Output Delay From CLKOUT Low GPOD CLKOUT GPP OUTPUT GPP O/D OUTPUT GPP INPUT t GPOD t GPOD t WFI Figure 26. General-Purpose Port Cycle Timing Rev Page October 2008 ADSP-BF538/ADSP-BF538F Min Max SCLK 0 6 Unit ns ns ...
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... ADSP-BF538/ADSP-BF538F Timer Cycle Timing Table 36 and Figure 27 describe timer expired operations. The input signal is asynchronous in “width capture mode” and “external clock mode” and has an absolute maximum input fre- quency MHz. SCLK Table 36. Timer Cycle Timing Parameter Timing Characteristics t Timer Pulse Width Input Low ...
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... System open-drain outputs: CANRX (when configured as PC1) and PC4. TCK TMS TDI TDO SYSTEM INPUTS t SYSTEM OUTPUTS 1 1 3,4 t TCK t t STAP HTAP t DTDO t t SSYS HSYS DSYS Figure 28. JTAG Port Timing Rev Page October 2008 ADSP-BF538/ADSP-BF538F Min Max Unit TCK ns ns ...
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... ADSP-BF538/ADSP-BF538F OUTPUT DRIVE CURRENTS Figure 29 through Figure 36 on Page 49 voltage characteristics for the output drivers of the ADSP- BF538/ADSP-BF538F processors. The curves represent the cur- rent drive capability of the output drivers as a function of output voltage. 120 100 100 0 0.5 1.0 1.5 SOURCE VOL TAGE (V) Figure 29 ...
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... V OH –40 –50 – –70 – DDEXT 3.5 4.0 ) DDEXT Rev Page October 2008 ADSP-BF538/ADSP-BF538F V = 2.25V 2.50V 2.75V 0.5 1.0 1.5 2.0 2.5 SOURCE VOLTAGE (V) Figure 37. Drive Current E (Low V ) DDEXT 0.5 1.0 1.5 2.0 2 SOURCE VOLTAGE (V) Figure 38. Drive Current E (High V ...
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... Example System Hold Time Calculation To determine the data output hold time in a particular system, first calculate t Figure the difference between the ADSP-BF538/ADSP-BF538F processor’s output voltage and the input threshold for the is 1.5 V for MEAS device requiring the hold time. C (per data line), and I (per data line) ...
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... Figure 44. Typical Output Rise and Fall Times (10% to 90%) vs. Load Capaci- 150 200 250 FALL TIME Figure 45. Typical Output Rise and Fall Times (10% to 90%) vs. Load Capaci- 150 200 250 Figure 46. Typical Output Rise and Fall Times (10% to 90%) vs. Load Rev Page October 2008 ADSP-BF538/ADSP-BF538F 12 10 RISE TIME ...
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... ADSP-BF538/ADSP-BF538F RISE TIME 100 LOAD CAPACITANCE (pF) Figure 47. Typical Output Rise and Fall Times (10% to 90%) vs. Load Capacitance for Driver DDEXT RISE TIME 100 LOAD CAPACITANCE (pF) Figure 48. Typical Output Rise and Fall Times (10% to 90%) vs. Load Capacitance for Driver DDEXT 14 12 RISE TIME ...
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... Table 39. Thermal Characteristics BC-316 With Flash Parameter JA can be used for a first JMA JMA Rev Page October 2008 ADSP-BF538/ADSP-BF538F Condition Typical 0 linear m/s air flow 21.6 1 linear m/s air flow 18.8 2 linear m/s air flow 18.1 5.36 0 linear m/s air flow 0.13 1 linear m/s air flow ...
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... Figure 52. 316-Ball CSP_BGA Ball Configuration (Top View FLASH CONTROL Figure 53. 316-Ball CSP_BGA Ball Configuration (Bottom View) Rev Page October 2008 GND VDDINT VDDRTC NC VDDEXT VROUTx FLASH CONTROL I/O Note: H18 and Y14 are NC for ADSP-BF538 and I/O (FCE and RESET) for ADSP-538F. A1 BALL ...
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... R18 J8 GND M12 GND R19 J9 GND M13 GND R20 J10 GND M14 V T1 DDINT J11 GND M18 TFS3 T2 Rev Page October 2008 ADSP-BF538/ADSP-BF538F Ball No. Signal M19 ABE0 T3 GND M20 ABE1 T7 V DDEXT TFS0 T8 V DDEXT DR0PRI T9 V DDEXT GND T10 V DDEXT ...
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... ADSP-BF538/ADSP-BF538F Table 41. 316-Ball CSP_BGA Ball Assignment (Alphabetically by Signal) Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal ABE0 M19 DATA8 Y6 ABE1 M20 DATA9 W6 ADDR1 N19 DATA10 Y5 ADDR2 N20 DATA11 W5 ADDR3 P19 DATA12 Y4 ADDR4 P20 DATA13 W4 ADDR5 R19 DATA14 Y3 ADDR6 ...
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... BSC SQ TOP VIEW 0.80 BSC DETAIL A DETAIL A SEATING PLANE BALL DIAMETER * COMPLIANT TO JEDEC STANDARDS MO-205-AM WITH EXCEPTION TO BALL DIAMETER. Figure 54. 316-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-316) Dimensions shown in millimeters Rev Page October 2008 ADSP-BF538/ADSP-BF538F A1 CORNER INDEX AREA ...
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... CSP_BGA (BC-316) ORDERING GUIDE Temperature 1 2 Model Range ADSP-BF538BBCZ-4A – +85 C 400 MHz ADSP-BF538BBCZ-5A – +85 C 533 MHz ADSP-BF538BBCZ-4F4 – +85 C 400 MHz ADSP-BF538BBCZ-4F8 – +85 C 400 MHz ADSP-BF538BBCZ-5F4 – +85 C 533 MHz ADSP-BF538BBCZ-5F8 – +85 C 533 MHz RoHS Compliant Part. 2 Referenced temperature is ambient temperature ...
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... Rev Page October 2008 ADSP-BF538/ADSP-BF538F ...
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... ADSP-BF538/ADSP-BF538F ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06700-0-10/08(B) Rev Page October 2008 ...