74HCT238D NXP Semiconductors, 74HCT238D Datasheet
74HCT238D
Specifications of 74HCT238D
Available stocks
Related parts for 74HCT238D
74HCT238D Summary of contents
Page 1
Rev. 03 — 16 July 2007 1. General description 74HC238 and 74HCT238 are high-speed Si-gate CMOS devices and are pin compatible with Low-Power Schottky TTL (LSTTL). The 74HC238/74HCT238 decoders accept three binary weighted address inputs ...
Page 2
... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74HC238N +125 C 74HC238D +125 C 74HC238DB +125 C 74HC238PW +125 C 74HC238BQ +125 C 74HCT238N +125 C 74HCT238D +125 C 74HCT238DB +125 C 74HCT238PW +125 C 74HCT238BQ +125 C 4. Functional diagram DECODER Fig 1. Logic symbol 74HC_HCT238_3 ...
Page 3
... NXP Semiconductors Fig 3. Logic diagram 5. Pinning information 5.1 Pinning 74HC238 74HCT238 GND 8 001aag755 Fig 4. Pin configuration DIP16, SO16, (T)SSOP16 74HC_HCT238_3 Product data sheet (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or input Fig 5. Pin confi ...
Page 4
... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol A[0: Y[0:7] GND Functional description [1] Table 3. Function table Inputs [ HIGH voltage level LOW voltage level don’t care. 74HC_HCT238_3 Product data sheet Pin 15, 14, 13, 12, 11, 10 Outputs Rev. 03 — 16 July 2007 74HC238; 74HCT238 ...
Page 5
... NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK I output clamping current OK I output current O I supply current CC I ground current ...
Page 6
... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74HC238 V HIGH-level input voltage LOW-level input voltage HIGH-level output voltage 4.0 mA 5.2 mA LOW-level output voltage 4.0 mA 5.2 mA input leakage ...
Page 7
... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I supply current 5 additional per input pin; CC supply current other inputs 4 5 inputs E1, E2 inputs E3 input C input I capacitance 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; test circuit see ...
Page 8
... NXP Semiconductors Table 7. Dynamic characteristics GND = 0 V; test circuit see Figure Symbol Parameter Conditions 74HCT238 t propagation delay An to Yn; see Yn; see see transition time see C power dissipation per package; PD capacitance V = GND [ the same as t and PHL PLH [ the same as t and THL ...
Page 9
... NXP Semiconductors Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 7. Input (E1, E2) to output (Yn) propagation delays and output transition times Table 8. Measurement points Type Input V M 74HC238 0.5V CC 74HCT238 1.3 V 74HC_HCT238_3 Product data sheet ...
Page 10
... NXP Semiconductors PULSE GENERATOR Test data is given in Table 9. Definitions for test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistance Test selection switch Fig 8. Load circuit for measuring switching times Table 9. Test data ...
Page 11
... NXP Semiconductors 12. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
Page 12
... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
Page 13
... NXP Semiconductors SSOP16: plastic shrink small outline package; 16 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT338-1 Fig 11. Package outline SOT338-1 (SSOP16) ...
Page 14
... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
Page 15
... NXP Semiconductors DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
Page 16
... Data sheet status Product data sheet • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Added type number 74HC238BQ and 74HCT238BQ (DHVQFN16 package) Product specifi ...
Page 17
... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
Page 18
... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 14 Revision history ...