74HCT109D NXP Semiconductors, 74HCT109D Datasheet - Page 2

• Manufacturer Part Number: 74HCT109D
• Description: LOGIC, 74HCT, JK FLIP-FLOP, SO16
• Manufacturer: NXP Semiconductors

Specifications of 74HCT109D

• Flip-flop Type: JK
• Propagation Delay: 20ns
• Frequency: 61MHz
• Output Current: 4mA
• Supply Voltage Range: 4.5V To 5.5V
• Logic Case Style: SOIC
• No. Of Pins: 16
• Operating: RoHS Compliant
• Trigger Type: Positive Edge
• Ic Output Type: Complementary
• Rohs Compliant: Yes

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT109 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT109 are dual positive-edge triggered, JK
flip-flops with individual J, K inputs, clock (CP) inputs, set
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
ORDERING INFORMATION
See
1997 Nov 25
t
f
C
C
PHL
max
J, K inputs for easy D-type flip-flop
Toggle flip-flop or “do nothing” mode
Output capability: standard
I
I
PD
Dual JK flip-flop with set and reset;
positive-edge trigger
CC
f
f
C
V
For HCT the condition is V
i
o
“74HC/HCT/HCU/HCMOS Logic Package Information”
/ t
SYMBOL
CC
PD
= input frequency in MHz
L
category: flip-flops
= output frequency in MHz
(C
PLH
= output load capacitance in pF
P
= supply voltage in V
is used to determine the dynamic power dissipation (P
L
D
= C
V
amb
CC
PD
2
= 25 C; t
V
f
o
CC
propagation delay
maximum clock frequency
input capacitance
power dissipation
) = sum of outputs
capacitance per flip-flop
2
nCP to nQ, nQ
nS
nR
D
D
f
r
i
to nQ, nQ
to nQ, nQ
= t
PARAMETER
I
I
f
= GND to V
= GND to V
= 6 ns
(C
L
V
CC
2
CC
CC
f
o
) where:
1.5 V.
notes 1 and 2
C
V
CC
L
= 15 pF;
= 5 V
2
.
(S
outputs.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input.
The J and K inputs control the state changes of the
flip-flops as described in the mode select function table.
The J and K inputs must be stable one set-up time prior to
the LOW-to-HIGH clock transition for predictable
operation.
The JK design allows operation as a D-type flip-flop by
tying the J and K inputs together.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
CONDITIONS
D
D
) and reset (R
in W):
D
) inputs; also complementary Q and Q
15
12
12
75
20
3.5
HC
TYPICAL
74HC/HCT109
Product specification
17
14
15
61
3.5
22
HCT
ns
ns
ns
MHz
pF
pF
UNIT