11LC010T-I/MNY Microchip Technology, 11LC010T-I/MNY Datasheet - Page 14

• Manufacturer Part Number: 11LC010T-I/MNY
• Description: IC, EEPROM, 1KBIT, SERIAL, 100KHZ TDFN-8
• Manufacturer: Microchip Technology

Specifications of 11LC010T-I/MNY

• Memory Size: 1Kbit
• Memory Configuration: 128 X 8 / 64 X 16
• Ic Interface Type: UNI/O
• Clock Frequency: 100kHz
• Supply Voltage Range: 2.5V To 5.5V
• Memory Case Style: TDFN
• No. Of Pins: 8
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 100kHz
• Interface: UNI/O™ (Single Wire)
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TDFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 11LC010T-I/MNYTR

11AAXXX/11LCXXX
4.5
The
register. The STATUS register may be read at any time,
even during a write cycle. The STATUS register is
formatted as follows:
The Write-In-Process (WIP) bit indicates whether the
11XX is busy with a write operation. When set to a ‘
a write is in progress, when set to a ‘
progress. This bit is read-only.
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When set to a ‘
allows writes to the array, when set to a ‘
prohibits writes to the array. This bit is set and cleared
using the WREN and WRDI instructions, respectively.
This bit is read-only for any other instruction.
FIGURE 4-6:
DS22067H-page 14
Note 1: For the 11XXXX1, this bit must be a ‘1’.
Note 2:
X
7
Note: Bits 4-7 are don’t cares, and will read as ‘
RDSR
SCIO
SCIO
X
6
The STATUS register data can continuously be read, or polled, by transmitting a MAK in place of the NoMAK.
Read Status Register (RDSR)
Instruction
X
5
instruction provides access to the STATUS
0
4
X
Standby Pulse
0
BP1
0
Command
3
READ STATUS REGISTER COMMAND SEQUENCE
0
0
BP0
1
2
0
1
0
WEL
’, no write is in
1
1
0
’, the latch
’, the latch
0
0
STATUS Register Data
Start Header
WIP
0
1
0
0
Preliminary
’.
1
0
0
’,
0
1
0
3 2 1 0
1
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user through the
These bits are nonvolatile.
The WIP and WEL bits will update dynamically (asyn-
chronous to issuing the
more, after the STATUS register data is received, the
master can provide a MAK during the Acknowledge
sequence to request that the data be transmitted again.
This allows the master to continuously monitor the WIP
and WEL bits without the need to issue another full
command.
Once the master is finished, it provides a NoMAK to
end the operation.
Note: If Read Status Register command is
Note: The current drawn for a Read Status
0
1
initiated while the 11XX is currently
executing an internal write cycle on the
STATUS
Protection bit values will be read during
the entire command.
Register command during a write cycle
is a combination of the I
Write operating currents.
1
0
Device Address
register,
1
 2010 Microchip Technology Inc.
0
RDSR
0
0
the
CC
instruction). Further-
0
WRSR
Read and I
0
new
(1)
instruction.
Block
CC