24AA00T-I/OTG Microchip Technology, 24AA00T-I/OTG Datasheet - Page 7

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24AA00T-I/OTG

Manufacturer Part Number
24AA00T-I/OTG
Description
IC, EEPROM 128BIT SERIAL 400KHZ SOT-23-5
Manufacturer
Microchip Technology
Datasheet

Specifications of 24AA00T-I/OTG

Memory Size
128bit
Memory Configuration
16 X 8
Ic Interface Type
I2C
Clock Frequency
400kHz
Supply Voltage Range
1.7V To 5.5V
Memory Case Style
SOT-23
No. Of Pins
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
7.0
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, then the Start bit and control byte
must be re-sent. If the cycle is complete, then the
device will return the ACK and the master can then
proceed with the next Read or Write command. See
Figure 7-1 for flow diagram.
FIGURE 7-2:
© 2007 Microchip Technology Inc.
SDA LINE
BUS ACTIVITY
MASTER
BUS ACTIVITY
x = “don’t care” bit
ACKNOWLEDGE POLLING
S
T
A
R
T
S
1
BYTE WRITE
0
1 0
Control
Byte
x
x
x
0
A
C
K
x
x x
Address
24AA00/24LC00/24C00
Word
x
FIGURE 7-1:
A
C
K
Initiate Write Cycle
Send Control Byte
Write Command
with R/W = 0
Acknowledge
Condition to
Send Stop
(ACK = 0)?
Did Device
Send Start
Operation
ACKNOWLEDGE
POLLING FLOW
Send
Next
Data
Yes
DS21178G-page 7
No
A
C
K
P
S
T
O
P

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