CAT25080YI-G CATALYST SEMICONDUCTOR, CAT25080YI-G Datasheet
CAT25080YI-G
Specifications of CAT25080YI-G
Available stocks
Related parts for CAT25080YI-G
CAT25080YI-G Summary of contents
Page 1
CAT25080, CAT25160 8-Kb and 16-Kb SPI Serial CMOS EEPROM Description The CAT25080/25160 are 8−Kb/16−Kb Serial CMOS EEPROM devices internally organized as 1024x8/2048x8 bits. They feature a 32−byte page write buffer and support the Serial Peripheral Interface (SPI) protocol. The device ...
Page 2
Table 1. ABSOLUTE MAXIMUM RATINGS Operating Temperature Storage Temperature Voltage on any Pin with Respect to Ground (Note 1) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions ...
Page 3
Table 5. A.C. CHARACTERISTICS Symbol Parameter f Clock Frequency SCK t Data Setup Time SU t Data Hold Time H t SCK High Time WH t SCK Low Time WL t HOLD to Output Low (Note 5) ...
Page 4
Pin Description SI: The serial data input pin accepts op−codes, addresses and data. In SPI modes (0,0) and (1,1) input data is latched on the rising edge of the SCK clock input. SO: The serial data output pin is used ...
Page 5
Table 8. STATUS REGISTER WPEN 0 0 Table 9. BLOCK PROTECTION BITS Status Register Bits BP1 BP0 Table 10. WRITE PROTECT CONDITIONS WPEN ...
Page 6
The CAT25080/160 device powers up into a write disable state. The device contains a Write Enable Latch (WEL) which must be set before attempting to write to the memory array or to the status register. In addition, the address of ...
Page 7
Byte Write Once the WEL bit is set, the user may execute a write sequence, by sending a WRITE instruction, a 16−bit address and data as shown in Figure 5. Only 10 significant address bits are used by the CAT25080 ...
Page 8
Write Status Register The Status Register is written by sending a WRSR instruction according to timing shown in Figure 7. Only bits 2, 3 and 7 can be written using the WRSR command SCK OPCODE ...
Page 9
Read from Memory Array To read from memory, the host sends a READ instruction followed by a 16−bit address (see Table 11 for the number of significant address bits). After receiving the last address bit, the CAT25080/160 will respond by ...
Page 10
Hold Operation The HOLD input can be used to pause communication between host and CAT25080/160. To pause, HOLD must be taken low while SCK is low (Figure 11). During the hold condition the device must remain selected (CS low). During ...
Page 11
PIN # 1 IDENTIFICATION D TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. PACKAGE DIMENSIONS PDIP−8, 300 mils CASE 646AA−01 ISSUE A SYMBOL ...
Page 12
PIN # 1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O SYMBOL ...
Page 13
E1 e TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O SYMBOL MIN A A1 0.05 A2 ...
Page 14
D E PIN#1 INDEX AREA TOP VIEW SYMBOL MIN NOM A 0.70 0.75 A1 0.00 0.02 A2 0.45 0.55 A3 0.20 REF b 0.20 0.25 D 1.90 2.00 D2 1.30 1.40 E 2.90 3.00 E2 1.20 1.30 e 0.50 TYP ...
Page 15
D E PIN #1 INDEX AREA TOP VIEW SYMBOL MIN NOM A 0.45 0.50 A1 0.00 0.02 b 0.18 0.25 D 1.90 2.00 D2 1.50 1.60 E 1.90 2.00 E2 0.80 0.90 e 0.50 BSC L 0.20 0.30 Notes: (1) ...
Page 16
Example of Ordering Information Prefix Device # Suffix CAT 25160 V Company ID Product Number 25080: 8−Kb 25160: 16−Kb Package L: PDIP V: SOIC, JEDEC Y: TSSOP VP2: TDFN ( mm) HU2: UDFN ( mm) 9. ...