25AA640AT-I/MNY Microchip Technology, 25AA640AT-I/MNY Datasheet - Page 10

• Manufacturer Part Number: 25AA640AT-I/MNY
• Description: IC, EEPROM, 64KBIT, SPI, 10MHZ, TDFN-8
• Manufacturer: Microchip Technology

Specifications of 25AA640AT-I/MNY

• Memory Size: 64Kbit
• Memory Configuration: 8K X 8
• Ic Interface Type: Serial, SPI
• Clock Frequency: 10MHz
• Access Time: 50ns
• Supply Voltage Range: 1.8V To 5.5V
• Memory Case Style: TDFN
• No. Of Pins: 8
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 10MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TDFN
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 25AA640AT-I/MNYTR

25AA640A/25LC640A
2.5
The Read Status Register instruction (RDSR) provides
access to the STATUS register. The STATUS register
may be read at any time, even during a write cycle. The
STATUS register is formatted as follows:
TABLE 2-2:
The Write-In-Process (WIP) bit indicates whether the
25XX640A is busy with a write operation. When set to
a ‘
is in progress. This bit is read-only.
FIGURE 2-6:
DS21830D-page 10
W/R = writable/readable. R = read-only.
WPEN
SCK
1
W/R
CS
SO
’, a write is in progress, when set to a ‘
7
SI
Read Status Register Instruction
(RDSR)
6
–
X
0
5
–
X
0
READ STATUS REGISTER TIMING SEQUENCE (RDSR)
STATUS REGISTER
X
4
–
0
1
W/R
BP1
High-Impedance
3
0
Instruction
2
W/R
BP0
0
2
3
0
WEL
4
R
1
0
’, no write
1
5
WIP
R
0
0
6
1
7
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read-only. When set to
a ‘
‘
this bit can always be updated via the WREN or WRDI
commands regardless of the state of write protection
on the STATUS register. These commands are shown
in Figure 2-4 and Figure 2-5.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile, and are shown in Table 2-3.
See Figure 2-6 for the RDSR timing sequence.
7
0
8
’, the latch prohibits writes to the array. The state of
1
’, the latch allows writes to the array, when set to a
6
9
Data from STATUS Register
10
5
11
4
© 2008 Microchip Technology Inc.
12
3
13
2
14
1
15
0