IDT7201LA35JG INTEGRATED DEVICE TECHNOLOGY, IDT7201LA35JG Datasheet - Page 9

• Manufacturer Part Number: IDT7201LA35JG
• Description: IC, FIFO 512X9, SMD, 7201, PLCC32
• Manufacturer: INTEGRATED DEVICE TECHNOLOGY

Specifications of IDT7201LA35JG

• Memory Size: 4.5Kbit
• Data Bus Width: 9bit
• Fifo Function: Asynchronous
• Clock Frequency: 22.2MHz
• Access Time: 35ns
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: PLCC
• No. Of Pins: 32
• Operating: RoHS Compliant
• Memory Configuration: 512 X 9
• Data Bus Direction: Bidirectional
• Rohs Compliant: Yes

OPERATING MODES:
each system (i.e. FF is monitored on the device where W is used; EF is monitored
on the device where R is used). For additional information, refer to Tech Note
8: Operating FIFOs on Full and Empty Boundary Conditions and Tech Note
6: Designing with FIFOs.
SINGLE DEVICE MODE
requirements are for 256/512/1,024 words or less. These devices are in a
Single Device Configuration when the Expansion In (XI) control input is
grounded (see Figure 12).
DEPTH EXPANSION
the requirements are for greater than 256/512/1,024 words. Figure 14
demonstrates Depth Expansion using three IDT7200/7201A/7202As. Any
HF
XO
XI
W
R
IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
W
W
R
R
A single IDT7200/7201A/7202A may be used when the application
The IDT7200/7201A/7202A can easily be adapted to applications when
Care must be taken to assure that the appropriate flag is monitored by
HALF-FULL OR LESS
LAST PHYSICAL
LOCATION
WRITE TO
t
t
XOL
XIS
t
XI
FIRST PHYSICAL
LOCATION
WRITE TO
t
WHF
t
XOH
Figure 9. Half-Full Flag Timing
t
XIR
Figure 10. Expansion Out
Figure 11. Expansion In
MORE THAN HALF-FULL
9
depth can be attained by adding additional IDT7200/7201A/7202As. These
FIFOs operate in the Depth Expansion mode when the following conditions
are met:
1. The first device must be designated by grounding the First Load (FL) control
2. All other devices must have FL in the HIGH state.
3. The Expansion Out (XO) pin of each device must be tied to the Expansion
4. External logic is needed to generate a composite Full Flag (FF) and Empty
5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in
FIFO Modules.
For additional information, refer to Tech Note 9: Cascading FIFOs or
input.
In (XI) pin of the next device. See Figure 14.
Flag (EF). This requires the ORing of all EFs and ORing of all FFs (i.e.
all must be set to generate the correct composite FF or EF). See Figure
14.
the Depth Expansion Mode.
LAST PHYSICAL
READ FROM
LOCATION
t
XIS
t
XOL
FIRST PHYSICAL
READ FROM
LOCATION
t
COMMERCIAL, INDUSTRIAL AND MILITARY
RHF
t
XOH
HALF-FULL OR LESS
TEMPERATURE RANGES
APRIL 3, 2006
2679 drw 12
2679 drw 11
2679 drw 13