PIC12F1822-I/MF Microchip Technology, PIC12F1822-I/MF Datasheet - Page 245

• Manufacturer Part Number: PIC12F1822-I/MF
• Description: IC, 8BIT MCU, PIC12, 32MHZ, DFN-8
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 12Fr

Specifications of PIC12F1822-I/MF

• Controller Family/series: PIC12
• No. Of I/o's: 6
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 128Byte
• Cpu Speed: 32MHz
• No. Of Timers: 3
• Core Size: 8 Bit
• Program Memory Size: 3.5KB
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 25-2:
 2010 Microchip Technology Inc.
Transmitter
Receiver
Master
Slave
Multi-master
Arbitration
Synchronization Procedure to synchronize the
Idle
Active
Addressed
Slave
Matching
Address
Write Request
Read Request
Clock Stretching When a device on the bus hold
Bus Collision
TERM
I
2
The device which shifts data out
onto the bus.
The device which shifts data in
from the bus.
The device that initiates a transfer,
generates clock signals and termi-
nates a transfer.
The device addressed by the mas-
ter.
A bus with more than one device
that can initiate data transfers.
Procedure to ensure that only one
master at a time controls the bus.
Winning arbitration ensures that
the message is not corrupted.
clocks of two or more devices on
the bus.
No master is controlling the bus,
and both SDA and SCL lines are
high.
Any time one or more master
devices are controlling the bus.
Slave device that has received a
matching address and is actively
being clocked by a master.
Address byte that is clocked into a
slave that matches the value
stored in SSP1ADD.
Slave receives a matching
address with R/W bit clear, and is
ready to clock in data.
Master sends an address byte with
the R/W bit set, indicating that it
wishes to clock data out of the
Slave. This data is the next and all
following bytes until a Restart or
Stop.
SCL low to stall communication.
Any time the SDA line is sampled
low by the module while it is out-
putting and expected high state.
C BUS TERMS
Description
PIC12F/LF1822/PIC16F/LF1823
Preliminary
25.4.5
The I
transition of SDA from a high to a low state while SCL
line is high. A Start condition is always generated by
the master and signifies the transition of the bus from
an Idle to an Active state.
forms for Start and Stop conditions.
A bus collision can occur on a Start condition if the
module samples the SDA line low before asserting it
low. This does not conform to the I
states no bus collision can occur on a Start.
25.4.6
A Stop condition is a transition of the SDA line from
low-to-high state while the SCL line is high.
25.4.7
A Restart is valid any time that a Stop would be valid.
A master can issue a Restart if it wishes to hold the
bus after terminating the current transfer. A Restart
has the same effect on the slave that a Start would,
resetting all slave logic and preparing it to clock in an
address. The master may want to address the same or
another slave.
In 10-bit Addressing Slave mode a Restart is required
for the master to clock data out of the addressed
slave. Once a slave has been fully addressed, match-
ing both high and low address bytes, the master can
issue a Restart and the high address byte with the
R/W bit set. The slave logic will then hold the clock
and prepare to clock out data.
After a full match with R/W clear in 10-bit mode, a prior
match flag is set and maintained. Until a Stop condi-
tion, a high address with R/W clear, or high address
match fails.
25.4.8
The SCIE and PCIE bits of the SSP1CON3 register
can enable the generation of an interrupt in Slave
modes that do not typically support this function. Slave
modes where interrupt on Start and Stop detect are
already enabled, these bits will have no effect.
Note: At least one SCL low time must appear
2
C specification defines a Start condition as a
STOP CONDITION
START/STOP CONDITION INTERRUPT
MASKING
before a Stop is valid, therefore, if the SDA
line goes low then high again while the SCL
line stays high, only the Start condition is
detected.
START CONDITION
RESTART CONDITION
Figure 25-10
2
C Specification that
DS41413B-page 245
shows wave