PIC16F1826-I/MQ Microchip Technology, PIC16F1826-I/MQ Datasheet - Page 283

• Manufacturer Part Number: PIC16F1826-I/MQ
• Description: IC, 8BIT MCU, PIC16F, 32MHZ, QFN-28
• Manufacturer: Microchip Technology

Specifications of PIC16F1826-I/MQ

• Controller Family/series: PIC16F
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 32MHz
• No. Of Timers: 3
• Interface: EUSART, I2C, SPI
• Core Size: 8 Bit
• Program Memory Size: 2kWords
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER 24-3:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0/0
GCEN
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I
set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).
GCEN: General Call Enable bit (in I
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR
0 = General call address disabled
ACKSTAT: Acknowledge Status bit (in I
1 = Acknowledge was not received
0 = Acknowledge was received
ACKDT: Acknowledge Data bit (in I
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1 = Not Acknowledge
0 = Acknowledge
ACKEN: Acknowledge Sequence Enable bit (in I
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDAx and SCLx pins, and transmit ACKDT data bit.
0 = Acknowledge sequence idle
RCEN: Receive Enable bit (in I
1 = Enables Receive mode for I
0 = Receive idle
PEN: Stop Condition Enable bit (in I
SCKx Release Control:
1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Stop condition Idle
RSEN: Repeated Start Condition Enabled bit (in I
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
SEN: Start Condition Enabled bit (in I
In Master mode:
1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
ACKSTAT
R-0/0
Automatically cleared by hardware.
SSPXCON2: SSPX CONTROL REGISTER 2
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-0/0
ACKDT
R/S/HC-0/0 R/S/HC-0/0
2
ACKEN
2
C Master mode only)
C
Preliminary
2
2
2
C mode only)
C Slave mode only)
C Master mode only)
2
C Master mode only)
2
C mode only)
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HC = Cleared by hardware
2
RCEN
C module is not in the Idle mode, this bit may not be
2
2
C Master mode only)
C Master mode only)
PIC16F/LF1826/27
R/S/HC-0/0
PEN
S = User set
R/S/HC-0/0
RSEN
DS41391B-page 283
R/W/HC-0/0
SEN
bit 0