ST7FLITE09Y0B6 FARNELL, ST7FLITE09Y0B6 Datasheet - Page 39

• Manufacturer Part Number: ST7FLITE09Y0B6
• Description: IC, 8BIT MCU, ST7, 16MHZ, DIP-16
• Manufacturer: FARNELL

Specifications of ST7FLITE09Y0B6

• Controller Family/series: ST7
• No. Of I/o's: 13
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 128Byte
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Core Size: 8 Bit
• Program Memory Size: 1.5 Kb
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

POWER SAVING MODES (Cont’d)
9.4 ACTIVE-HALT AND HALT MODES
ACTIVE-HALT and HALT modes are the two low-
est power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruc-
tion. The decision to enter either in ACTIVE-HALT
or HALT mode is given by the LTCSR/ATCSR reg-
ister status as shown in the following table:.
9.4.1 ACTIVE-HALT MODE
ACTIVE-HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ in-
struction when active halt mode is enabled.
The MCU can exit ACTIVE-HALT mode on recep-
tion of a Lite Timer / AT Timer interrupt or a RE-
SET.
– When exiting ACTIVE-HALT mode by means of
– When exiting ACTIVE-HALT mode by means of
When entering ACTIVE-HALT mode, the I bit in
the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately.
In ACTIVE-HALT mode, only the main oscillator
and the selected timer counter (LT/AT) are running
to keep a wake-up time base. All other peripherals
are not clocked except those which get their clock
supply from another clock generator (such as ex-
ternal or auxiliary oscillator).
Caution: As soon as ACTIVE-HALT is enabled,
executing a HALT instruction while the Watchdog
is active does not generate a RESET if the
WDGHALT bit is reset.
This means that the device cannot spend more
than a defined delay in this power saving mode.
TBIE bit
LTCSR
a RESET, a 256 CPU cycle delay occurs. After
the start up delay, the CPU resumes operation
by fetching the reset vector which woke it up (see
Figure
an interrupt, the CPU immediately resumes oper-
ation by servicing the interrupt vector which woke
it up (see
0
0
0
1
x
26).
ATCSR
OVFIE
bit
Figure
0
1
1
x
x
CK1 bit
ATCSR
26).
1
0
x
x
x
CK0 bit
ATCSR
0
1
1
x
x
ACTIVE-HALT
mode disabled
ACTIVE-HALT
mode enabled
Meaning
Figure 25. ACTIVE-HALT Timing Overview
Figure 26. ACTIVE-HALT Mode Flow-chart
Notes:
1. This delay occurs only if the MCU exits ACTIVE-
HALT mode by means of a RESET.
2. Peripherals clocked with an external clock
source can still be active.
3. Only the Lite Timer RTC and AT Timer interrupts
can exit the MCU from ACTIVE-HALT mode.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
[Active Halt Enabled]
INSTRUCTION
HALT INSTRUCTION
RUN
(Active Halt enabled)
N
HALT
INTERRUPT
ACTIVE
HALT
Y
ST7LITE0xY0, ST7LITESxY0
CYCLE DELAY
INTERRUPT
3)
256 CPU
RESET
OR SERVICE INTERRUPT
256 CPU CLOCK CYCLE
FETCH RESET VECTOR
OR
OSCILLATOR
PERIPHERALS
OSCILLATOR
PERIPHERALS
OSCILLATOR
PERIPHERALS
CPU
I BIT
CPU
I BIT
CPU
I BITS
N
DELAY
RESET
Y
1)
VECTOR
FETCH
RUN
2)
2)
OFF
OFF
OFF
ON
ON
ON
X
ON
ON
ON
X
0
4)
4)
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