AD7719BRUZ Analog Devices Inc, AD7719BRUZ Datasheet - Page 30

• Manufacturer Part Number: AD7719BRUZ
• Description: Dual 16-Bit & 24-Bit SD ADC
• Manufacturer: Analog Devices Inc

Specifications of AD7719BRUZ

• Number Of Bits: 16/24
• Sampling Rate (per Second): 105
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 4.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7719EB - BOARD EVAL FOR AD7719
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD7719
AD7719-to-ADSP-2103/ADSP-2105 Interface
Figure 14 shows an interface between the AD7719 and the
ADSP-2103/ADSP-2105 DSP processor. In the interface shown,
the RDY bits of the Status register are again monitored to
determine when the Data register is updated. The alternative
scheme is to use an interrupt-driven system, in which case the
RDY output is connected to the IRQ2 input of the ADSP-2103/
ADSP-2105. The serial interface of the ADSP-2103/ADSP-2105
is set up for alternate framing mode. The RFS and TFS pins
of the ADSP-2103/ADSP-2105 are configured as active low
outputs and the ADSP-2103/ADSP-2105 serial clock line, SCLK,
is also configured as an output. The CS for the AD7719 is active
when either the RFS or TFS outputs from the ADSP-2103/
ADSP-2105 are active. The serial clock rate on the ADSP-2103/
ADSP-2105 should be limited to 3 MHz to ensure correct opera-
tion with the AD7719.
CIRCUIT DESCRIPTION
The AD7719 is a Σ-∆ A/D converter incorporating two indepen-
dent Σ-∆ A/D converters with on-chip digital filtering, intended
for the measurement of wide dynamic range, low frequency
signals such as those in weigh scale, pressure, temperature,
industrial control, or process control applications.
The main ADC is intended to convert the primary sensor input.
The main ADC employs a Σ-∆ conversion technique to realize up
to 24 bits of no-missing-codes performance. The Σ-∆ modulator
converts the sampled input signal into a digital pulse train whose
duty cycle contains the digital information. A Sinc
low-pass filter is then employed to decimate the modulator output
data stream to give a valid data conversion result at program-
mable output rates from 5.35 Hz (186.77 ms) to 105.03 Hz
(9.52 ms). A Chopping scheme is also employed to minimize
ADC offset and offset and gain drift errors. The analog input
to the main ADC can be operated in buffered or unbuffered
mode and can be programmed for one of eight input ranges from
±20 mV to ±2.56 V. The input channels can be configured for
either fully differential inputs or pseudodifferential input
channels via the CH1 and CH0 bits in the main ADC control
register (AD0CON) and the CHCON bit in the mode register.
When configured for buffered mode (BUF = 0), the input channels
are internally buffered, allowing the part to handle significant
source impedances on the analog input, allowing R/C filtering
(for noise rejection or RFI reduction) to be placed on the analog
inputs if required. When operating in unbuffered mode, care has
to be exercised when selecting front end source impedances so
Figure 14. AD7719-to-ADSP-2103/ADSP-2105 Interface
ADSP-2103 /
ADSP-2105
SCLK
RFS
TFS
DR
DT
DV
DD
RESET
CS
DOUT
DIN
SCLK
AD7719
3
programmable
–30–
as not to introduce gain errors. On-chip burnout currents are
available and can be used to check that a transducer on the
selected channel is still operational before attempting to take
measurements.
The second or auxiliary ADC is intended to convert secondary
inputs such as those from a cold junction diode or thermistor.
This ADC is unbuffered and has a fixed input range of 0 V
to REFIN2 (ARN bit = 1) or 0 to REFIN2/2 (ARN bit = 0).
Again, this ADC can be configured for differential or pseudo-
differential inputs via the ACH2, ACH1, and ACH0 bits in the
auxiliary ADC control register (AD1CON). The auxiliary ADC
is specified for 16-bit performance and, since its analog inputs
are unbuffered, care must be exercised when placing filtering on
the front end to avoid introducing gain errors into the measure-
ment system.
The basic connection diagram for the AD7719 is shown in
Figure 15. This shows both the AV
AD7719 being driven from the analog 5 V supply. Some appli-
cations will have AV
AV
allowing the device to be operated with 5 V analog supply and
3 V digital supply or vice versa. An AD780/REF195 precision
2.5 V reference provides the reference source for the part. A
quartz crystal or ceramic resonator provides the 32 kHz master
clock source for the part. In some cases, it will be necessary to
connect capacitors on the crystal or resonator to ensure that it
does not oscillate at overtones of its fundamental operating
frequency. The values of capacitors will vary depending on the
manufacturer’s specifications.
ANALOG 5V
ANALOG 5V
SUPPLY
DD
SUPPLY
V
REF195
AD780/
IN
and DV
GND
V
OUT
10 F
Figure 15. Basic Connection Diagram
0.1 F
10 F
DD
can be operated independently of each other,
DD
IOUT1
IOUT2
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
REFIN1(+)
REFIN2
REFIN1(–)
PWRGND
and DV
0.1 F
DD
AGND
AV
AD7719
DD
driven from separate supplies.
DD
DV
DGND
and DV
DD
P1/SW1
P2/SW2
RESET
XTAL1
XTAL2
DOUT
SCLK
0.1 F
DIN
CS
DD
P3
P4
pins of the
32kHz
CRYSTAL
5V
REV. A
CHIP
SELECT
RECEIVE
(READ)
SERIAL
DATA
(WRITE)
SERIAL
CLOCK