CDB4364 Cirrus Logic Inc, CDB4364 Datasheet - Page 29

• Manufacturer Part Number: CDB4364
• Description: Eval Bd 6Chn DAC W/DSD Spt&Lw-Ltnc DF
• Manufacturer: Cirrus Logic Inc

Specifications of CDB4364

• Number Of Dac's: 6
• Number Of Bits: 24
• Outputs And Type: 6, Single Ended
• Sampling Rate (per Second): 192k
• Data Interface: Serial
• Dac Type: Voltage
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS4364
• Description/function: Audio D/A
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS4364
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant

DS619F1
4.13
4.14
4.14.1 MAP Auto Increment
4.14.2 I²C Mode
Recommended Procedure for Switching Operational Modes
For systems where the absolute minimum in clicks and pops is required, it is recommended that the MUTE
bits are set prior to changing significant DAC functions (such as changing sample rates or clock sources).
The mute bits may then be released after clocks have settled and the proper modes have been set.
It is required to have the device held in reset if the minimum high/low time specs of MCLK can not be met
during clock source changes.
Control Port Interface
The control port is used to load all the internal register settings in order to operate in Software Mode (see
the
with the audio sample rate. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
The control port operates in one of two modes:
4.14.2.1 I²C Write
To write to the device, follow the procedure below while adhering to the control port Switching Specifica-
tions in
1.
2. Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP. This
3. Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed to by
4. If the INCR bit (see
5. If the INCR bit is set to 0 and further
4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µs.
The device has MAP (memory address pointer) auto increment capability enabled by the INCR bit (also
the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive
SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or
writes of successive registers.
In the
control port clock, SCL (see
ables the user to alter the chip address (001100[AD0][R/W]) and should be tied to VLC or GND as re-
quired, before powering up the device. If the device ever detects a high to low transition on the AD0/CS
pin after power-up, SPI Mode will be selected.
“Parameter Definitions” on page
001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth
bit of the address byte is the R/W bit.
byte points to the register to be written.
the MAP.
are written, then initiate a STOP condition to the bus.
a repeated START condition and follow the procedure detailed from step 1. If no further writes to other
registers are desired, initiate a STOP condition to the bus.
Initiate a START condition to the
converted incorrectly by the Hardware Mode settings).
I²C
Section
Mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial
2.
Section
Figure 22
4.14.1) is set to 1, repeat the previous step until all the desired registers
47). The operation of the control port may be completely asynchronous
I²C
for the clock to data relationship). There is no CS pin. Pin AD0 en-
I²C
bus followed by the address byte. The upper 6 bits must be
writes to other registers are desired, it is necessary to initiate
I²C
or SPI.
I²C
writes or reads and
CS4364
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