MC100LVEL14DW ON Semiconductor, MC100LVEL14DW Datasheet

MC100LVEL14DW

Manufacturer Part Number

MC100LVEL14DW

Description

Clock Generator / Distributor Logic IC

Manufacturer

ON Semiconductor

Datasheets

1.MC100LVEL14DW.pdf (6 pages)

2.MC100LVEL14DW.pdf (4 pages)

Specifications of MC100LVEL14DW

Digital Ic Case Style

SOIC

No. Of Pins

Operating Temperature Range

-40Â°C To +85Â°C

Logic Type

Clock Distribution

Mounting Type

Surface Mount

Peak Reflow Compatible (260 C)

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

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MC100LVEL14

3.3V ECL 1:5 Clock

Distribution Chip

Description

designed explicitly for low skew clock distribution applications. The

device can be driven by either a differential or single-ended ECL or, if

positive power supplies are used, PECL input signal. The LVEL14 is

functionally and pin compatible with the EL14 but is designed to

operate in ECL or PECL mode for a voltage supply range of −3.0 V to

−3.8 V ( or 3.0 V to 3.8 V).

distribution of a lower speed scan or test clock along with the high speed

system clock. When LOW (or left open and pulled LOW by the input

pulldown resistor) the SEL pin will select the differential clock input.

be enabled/disabled when they are already in the LOW state. This

avoids any chance of generating a runt clock pulse when the device is

enabled/disabled as can happen with an asynchronous control. The

internal flip flop is clocked on the falling edge of the input clock,

therefore all associated specification limits are referenced to the

negative edge of the clock input.

this device only. For single−ended input conditions, the unused

differential input is connected to V

mA. When not used, V

Features

•

*For additional information on our Pb−Free strategy and soldering details, please

November, 2006 − Rev. 8

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

The MC100LVEL14 is a low skew 1:5 clock distribution chip

The LVEL14 features a multiplexed clock input to allow for the

The common enable (EN) is synchronous so that the outputs will only

The V

For Additional Information, see Application Note AND8003/D

Oxygen Index: 28 to 34

50 ps Output-to-Output Skew

Synchronous Enable/Disable

Multiplexed Clock Input

ESD Protection: Human Body Model >2 kV

The 100 Series Contains Temperature Compensation

PECL Mode Operating Range:

NECL Mode Operating Range:

Internal Input Pulldown Resistors on CLK

Q Output will Default LOW with Inputs Open or at V

Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

Moisture Sensitivity Level 1

Flammability Rating: UL 94 V−0 @ 0.125 in,

Transistor Count = 303 devices

Pb−Free Packages are Available*

may also rebias AC coupled inputs. When used, decouple V

via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5

= 3.0 V to 3.8 V with V

= 0 V with V

pin, an internally generated voltage supply, is available to

= −3.0 V to −3.8 V

should be left open.

= 0 V

as a switching reference voltage.

and

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

DW SUFFIX

CASE 751D

SOIC−20

ORDERING INFORMATION

http://onsemi.com

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

Publication Order Number:

AWLYYWWG

100LVEL14

MARKING

DIAGRAM

MC100LVEL14/D

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