PIC16F946-E/PT Microchip Technology, PIC16F946-E/PT Datasheet
PIC16F946-E/PT
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PIC16F946-E/PT Summary of contents
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... LCD Driver and nanoWatt Technology © 2005 Microchip Technology Inc. PIC16F946 Data Sheet 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with Preliminary DS41265A ...
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... PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Programmable code protection • High-Endurance Flash/EEPROM cell: - 100,000 write Flash endurance - 1,000,000 write EEPROM endurance - Flash/Data EEPROM retention: > 40 years © 2005 Microchip Technology Inc. PIC16F946 Low-Power Features: • Standby Current: - <100 nA @ 2.0V, typical • Operating Current kHz, 2.0V, typical - 100 MHz, 2.0V, typical • ...
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... PIC16F946 Program Data Memory Memory Device Flash SRAM (words) (bytes) PIC16F946 8K 336 Pin Diagram – PIC16F946 TQFP RD6/SEG19 1 RD7/SEG20 2 RG0/SEG36 3 RG1/SEG37 4 RG2/SEG38 5 RG3/SEG39 6 RG4/SEG40 7 RG5/SEG41 RF0/SEG32 RF1/SEG33 12 RF2/SEG34 13 RF3/SEG35 14 RB0/INT/SEG0 15 RB1/SEG1 DS41265A-page 2 10-bit A/D I/O (segment (ch) EEPROM drivers) (bytes) 256 PIC16F946 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2005 Microchip Technology Inc. Preliminary PIC16F946 DS41265A-page 3 ...
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... PIC16F946 NOTES: DS41265A-page 4 Preliminary © 2005 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device specific information for the PIC16F946. Additional information may be found in ® the “PICmicro Mid-Range MCU Family Reference Manual” (DS33023), downloaded from the Microchip web site. The Reference Manual should be considered a complementary document to this data sheet and is ...
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... PIC16F946 FIGURE 1-1: PIC16F946 BLOCK DIAGRAM Configuration 13 Program Counter Flash Program 8-Level Stack (13-bit) Memory Program 14 Program Memory Read Bus Instruction Reg Direct Addr 8 Power-up Timer Oscillator Instruction Start-up Timer Decode and Power-on Control Reset OSC1/CLKI Watchdog Timer Timing OSC2/CLKO Generation ...
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... TABLE 1-1: PIC16F946 PINOUT DESCRIPTIONS Name Function RA0/AN0/C1-/SEG12 RA0 AN0 C1- SEG12 RA1/AN1/C2-/SEG7 RA1 AN1 C2- SEG7 RA2/AN2/C2+/V -/COM2 RA2 REF AN2 C2+ V REF COM2 RA3/AN3/C1+/V +/SEG15 RA3 REF AN3 C1+ V REF SEG15 RA4/C1OUT/T0CKI/SEG4 RA4 C1OUT T0CKI SEG4 RA5/AN4/C2OUT/SS/SEG5 RA5 AN4 ...
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... PIC16F946 TABLE 1-1: PIC16F946 PINOUT DESCRIPTIONS (CONTINUED) Name Function RB3/SEG3 RB3 SEG3 RB4/COM0 RB4 COM0 RB5/COM1 RB5 COM1 RB6/ICSPCLK/ICDCK/SEG14 RB6 ICSPCLK ICDCK SEG14 RB7/ICSPDAT/ICDDAT/SEG13 RB7 ICSPDAT ICDDAT SEG13 RC0/VLCD1 RC0 VLCD1 RC1/VLCD2 RC1 VLCD2 RC2/VLCD3 RC2 VLCD3 RC3/SEG6 RC3 SEG6 RC4/T1G/SDO/SEG11 ...
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... TABLE 1-1: PIC16F946 PINOUT DESCRIPTIONS (CONTINUED) Name Function RC7/RX/DT/SDI/SDA/SEG8 RC7 RX DT SDI SDA SEG8 RD0/COM3 RD0 COM3 RD1 RD1 RD2/CCP2 RD2 CCP2 RD3/SEG16 RD3 SEG16 RD4/SEG17 RD4 SEG17 RD5/SEG18 RD5 SEG18 RD6/SEG19 RD6 SEG19 RD7/SEG20 RD7 SEG20 RE0/AN5/SEG21 RE0 AN5 SEG21 ...
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... PIC16F946 TABLE 1-1: PIC16F946 PINOUT DESCRIPTIONS (CONTINUED) Name Function RF1/SEG33 RF1 SEG33 RF2/SEG34 RF2 SEG34 RF3/SEG35 RF3 SEG35 RF4/SEG28 RF4 SEG28 RF5/SEG29 RF5 SEG29 RF6/SEG30 RF6 SEG30 RF7/SEG31 RF7 SEG31 RG0/SEG36 RG0 SEG36 RG1/SEG37 RG1 SEG37 RG2/SEG38 RG2 SEG38 RG3/SEG39 RG3 ...
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... GENERAL PURPOSE REGISTER 0000h FILE The register file is organized as 336 the 0004h PIC16F946. Each register is accessed either directly or 0005h indirectly through the File Select Register (FSR) (see Section 2.5 “Indirect Addressing, INDF and FSR 07FFh Registers”). 0800h 2 ...
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... PIC16F946 FIGURE 2-2: PIC16F946 SPECIAL FUNCTION REGISTERS File Address (1) Indirect addr. 00h Indirect addr. TMR0 01h OPTION_REG 81h PCL 02h PCL STATUS 03h STATUS FSR 04h FSR PORTA 05h TRISA PORTB 06h TRISB PORTC 07h TRISC PORTD 08h TRISD PORTE 09h ...
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... TABLE 2-1: PIC16F946 SPECIAL REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 01h TMR0 Timer0 Module Register 02h PCL Program Counter’s (PC) Least Significant Byte 03h STATUS ...
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... PIC16F946 TABLE 2-2: PIC16F946 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION_REG RBPU INTEDG 82h PCL Program Counter’s (PC) Least Significant Byte 83h ...
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... TABLE 2-3: PIC16F946 SPECIAL REGISTERS SUMMARY BANK 2 Addr Name Bit 7 Bit 6 Bank 2 100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 101h TMR0 Timer0 Module Register 102h PCL Program Counter’s (PC) Least Significant Byte 103h STATUS ...
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... PIC16F946 TABLE 2-4: PIC16F946 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3 Addr Name Bit 7 Bit 6 Bank 3 180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 181h OPTION_REG RBPU INTEDG 182h PCL Program Counter (PC) Least Significant Byte 183h STATUS ...
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... Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. R/W-0 R-1 R-1 RP1 RP0 Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F946 R/W-x R/W-x R/W bit 0 (1) ( Bit is unknown DS41265A-page 17 ...
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... PIC16F946 2.2.2.2 Option Register The Option register is a readable and writable register, which contains various control bits to configure: • TMR0/WDT prescaler • External RB0/INT interrupt • TMR0 • Weak pull-ups on PORTB REGISTER 2-2: OPTION_REG – OPTION REGISTER (ADDRESS: 81h OR 181h) R/W-1 ...
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... R/W-0 R/W-0 R/W-0 PEIE T0IE INTE RBIE (1) ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F946 R/W-0 R/W-0 R/W-x T0IF INTF RBIF bit Bit is unknown DS41265A-page 19 ...
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... PIC16F946 2.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as shown in Register 2-1. REGISTER 2-4: PIE1 – PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch) R/W-0 R/W-0 EEIE ADIE bit 7 bit 7 EEIE: EE Write Complete Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 ADIE: A/D Converter Interrupt Enable bit ...
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... Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. R/W-0 R/W-0 U-0 C2IE C1IE LCDIE — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F946 R/W-0 U-0 R/W-0 LVDIE — CCP2IE bit Bit is unknown DS41265A-page 21 ...
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... PIC16F946 2.2.2.6 PIR1 Register The PIR1 register contains the interrupt flag bits, as shown in Register 2-6. REGISTER 2-6: PIR1 – PERIPHERAL INTERRUPT REQUEST REGISTER 1 (ADDRESS: 0Ch) R/W-0 R/W-0 EEIF ADIF bit 7 bit 7 EEIF: EE Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) ...
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... R-0 R-0 U-0 C2IF C1IF LCDIF — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F946 R/W-0 U-0 R/W-0 LVDIF — CCP2IF bit Bit is unknown DS41265A-page 23 ...
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... PIC16F946 2.2.2.8 PCON Register The Power Control (PCON) register (See Register 2-8) contains flag bits to differentiate between a: • Power-on Reset (POR) • Brown-out Reset (BOR) • Watchdog Timer Reset (WDT) • External MCLR Reset The PCON register also controls the software enable of the BOR ...
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... Application Note AN556, “Implementing a Table Read” (DS00556). 2.3.2 STACK The PIC16F946 has an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch ...
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... An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-4. A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 2-2. FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC16F946 Direct Addressing From Opcode RP1 RP0 6 ...
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... STATUS,RP1 MOVLW 07h MOVWF CMCON0 CLF ANSEL MOVLW F0h MOVWF TRISA BCF STATUS,RP0 BCF STATUS,RP1 is TRISA Preliminary PIC16F946 INITIALIZING PORTA ;Bank 0 ; ;Init PORTA ;Bank 1 ; ;Set RA<2:0> to ;digital I/O ;Make all PORTA I/O ;Set RA<7:4> as inputs ;and set RA<3:0> outputs ;Bank 0 ; DS41265A-page 27 ...
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... PIC16F946 REGISTER 3-1: PORTA – PORTA REGISTER (ADDRESS: 05h) R/W-x R/W-x RA7 bit 7 bit 7-0 RA<7:0>: PORTA I/O Pin bits 1 = Port pin is > Port pin is <V Legend Readable bit - n = Value at POR REGISTER 3-2: TRISA – PORTA TRI-STATE REGISTER (ADDRESS: 85h) R/W-1 ...
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... Data Bus D WR PORTA CK Data Latch D WR TRISA CK TRIS Latch RD TRISA SEG12 © 2005 Microchip Technology Inc Analog Input or SE12 and LCDEN SE12 and LCDEN RD PORTA SE12 and LCDEN To A/D Converter or Comparator Preliminary PIC16F946 V DD I/O Pin TTL Input Buffer DS41265A-page 29 ...
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... PIC16F946 3.1.1.2 RA1/AN1/C2-/SEG7 Figure 3-2 shows the diagram for this pin. The RA1/AN1/C2-/SEG7 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the A/D • an analog input for Comparator 2 • an analog output for the LCD ...
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... D WR TRISA CK TRIS Latch RD TRISA COM2 To A/D Converter or Comparator To A/D Module V © 2005 Microchip Technology Inc. -/COM2 REF LCDEN and LMUX<1:0> PORTA LCDEN and LMUX<1:0> Input REF Preliminary PIC16F946 V DD I/O Pin Analog Input or LCDEN and LMUX<1:0> TTL Input Buffer DS41265A-page 31 ...
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... PIC16F946 3.1.1.4 RA3/AN3/C1+/V +/SEG15 REF Figure 3-4 shows the diagram for this pin. The RA3/AN3/C1+/V +/COM3/SEG15 REF configurable to function as one of the following: • a general purpose input • an analog input for the A/D • a voltage reference input for the A/D • analog outputs for the LCD ...
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... Data Latch D WR TRISA CK TRIS Latch RD TRISA T0CKI SEG4 © 2005 Microchip Technology Inc. C1OUT Analog Input or SE4 and LCDEN SE4 and LCDEN RD PORTA Schmitt Trigger SE4 and LCDEN Preliminary PIC16F946 V DD I/O Pin V SS TTL Input Buffer SE4 and LCDEN DS41265A-page 33 ...
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... PIC16F946 3.1.1.6 RA5/AN4/C2OUT/SS/SEG5 Figure 3-6 shows the diagram for this pin. The RA5/AN4/C2OUT/SS/SEG5 pin is configurable to function as one of the following: • a general purpose I/O • a digital output from Comparator 2 • a slave select input • an analog output for the LCD • an analog input for the A/D ...
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... WR PORTA CK Q Data Latch TRISA CK Q TRIS Latch F = 00x, 010 OSC or T1OSCEN RD TRISA RD PORTA © 2005 Microchip Technology Inc. From OSC1 F = 1x1 OSC /4) OSC 00x, 010 OSC or T1OSCEN Input Buffer Preliminary PIC16F946 Oscillator Circuit V DD RA6/OSC2/ CLKO/T1OSO Pin V SS TTL DS41265A-page 35 ...
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... PIC16F946 3.1.1.8 RA7/OSC1/CLKI/T1OSI Figure 3-8 shows the diagram for this pin. The RA7/OSC1/CLKI/T1OSI pin is configurable to function as one of the following: • a general purpose I/O • a crystal/resonator connection • a clock input • a TMR1 oscillator connection FIGURE 3-8: BLOCK DIAGRAM OF RA7/OSC1/CLKI/T1OSI Data Bus PORTA ...
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... Q2 cycle), then the RBIF interrupt flag may not get set. Furthermore, since a read or write on a port affects all bits of that port, care must be taken when using multiple pins in Interrupt-on-change mode. Changes on one pin may not be seen while servicing changes on another pin. Preliminary PIC16F946 DS41265A-page 37 ...
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... PIC16F946 REGISTER 3-3: PORTB – PORTB REGISTER (ADDRESS: 06h OR 106h) R/W-x R/W-x RB7 bit 7 bit 7-0 RB<7:0>: PORTB I/O Pin bits 1 = Port pin is > Port pin is <V Legend Readable bit - n = Value at POR REGISTER 3-4: TRISB – PORTB TRI-STATE REGISTER (ADDRESS: 86h, 186h) ...
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... Value at POR © 2005 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 R/W-1 WPUB5 WPUB4 WPUB3 WPUB2 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F946 R/W-1 R/W-1 WPUB1 WPUB0 bit Bit is unknown DS41265A-page 39 ...
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... PIC16F946 3.3.3 PIN DESCRIPTIONS AND DIAGRAMS Each PORTB pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the LCD or interrupts, refer to the appropriate section in this data sheet. 3.3.3.1 RB0/INT/SEG0 Figure 3-9 shows the diagram for this pin ...
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... To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 2: RB0 only. © 2005 Microchip Technology Inc. SE<3:0> SE<3:0> and LCDEN TTL Input Buffer RD PORTB SE<3:0> and LCDEN SE0 and LCDEN Schmitt Trigger Preliminary PIC16F946 Weak DD P Pull-up I/O Pin DS41265A-page 41 ...
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... PIC16F946 3.3.3.5 RB4/COM0 Figure 3-10 shows the diagram for this pin. The RB4/COM0 pin is configurable to function as one of the following: • a general purpose I/O • an analog output for the LCD FIGURE 3-10: BLOCK DIAGRAM OF RB4/COM0 (1) RBPU Data Bus PORTB CK Data Latch TRISB ...
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... To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. © 2005 Microchip Technology Inc. LCDEN and LMUX<1:0> 00 LCDEN and LMUX<1:0> 00 TTL Input Buffer LCDEN and LMUX<1:0> Preliminary PIC16F946 Weak DD P Pull-up I/O Pin OSC D RD PORTB DS41265A-page 43 ...
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... PIC16F946 3.3.3.7 RB6/ICSPCLK/ICDCK/SEG14 Figure 3-12 shows the diagram for this pin. The RB6/ICSPCLK/ICDCK/SEG14 pin is configurable to function as one of the following: • a general purpose I/O • an In-Circuit Serial Programming™ clock • an ICD clock I/O • an analog output for the LCD FIGURE 3-12: ...
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... To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. © 2005 Microchip Technology Inc. ( Input Buffer SE13 and LCDEN Q Q Program Mode/ICD Schmitt Trigger Buffer SE13 and LCDEN Preliminary PIC16F946 V DD Weak P Pull- I/O Pin TTL PORTB OSC ...
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... PIC16F946 TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Address Name Bit 7 Bit 6 06h/106h PORTB RB7 RB6 86h/186h TRISB TRISB7 TRISB6 0Bh/8Bh/ INTCON GIE PEIE 10Bh/18Bh 95h WPUB WPUB7 WPUB6 96h IOCB IOCB7 IOCB6 107h LCDCON LCDEN SLPEN (1) 11Ch LCDSE0 SE7 SE6 ...
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... Bit is cleared R/W-1 R/W-1 R/W-1 TRISC5 TRISC4 TRISC3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F946 INITIALIZING PORTC ;Init PORTC ;Set RC<7:0> as inputs ; ;Disable VLCD<3:1> ;inputs on RC<2:0> R/W-x R/W-x R/W-x RC2 RC1 ...
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... PIC16F946 3.4.1 PIN DESCRIPTIONS AND DIAGRAMS Each PORTC pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the LCD or SSP, refer to the appropriate section in this data sheet. 3.4.1.1 RC0/VLCD1 Figure 3-14 shows the diagram for this pin ...
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... BLOCK DIAGRAM OF RC2/VLCD3 Data Bus PORTC CK Q Data Latch TRISC Q CK TRIS Latch RD TRISC RD PORTC VLCD3 © 2005 Microchip Technology Inc. (VLCDEN and LMUX<1:0> 00) (VLCDEN and LMUX<1:0> 00) VLCDEN Schmitt Trigger VLCDEN Preliminary PIC16F946 V DD RC1/VLCD2 Pin Schmitt Trigger V DD RC2/VLCD3 Pin DS41265A-page 49 ...
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... PIC16F946 3.4.1.4 RC3/SEG6 Figure 3-17 shows the diagram for this pin. The RC3/SEG6 pin is configurable to function as one of the following: • a general purpose I/O • an analog output for the LCD FIGURE 3-17: BLOCK DIAGRAM OF RC3/SEG6 Data Bus PORTC Q CK Data Latch TRISC ...
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... BLOCK DIAGRAM OF RC4/T1G/SDO/SEG11 PORT/SDO Select Data Bus PORTC CK Q Data Latch TRISC CK Q TRIS Latch RD TRISC RD PORTC Timer1 Gate SEG11 © 2005 Microchip Technology Inc. SDO 0 1 SE11 and LCDEN SE11 and LCDEN Preliminary PIC16F946 V DD RC4/T1G/ SDO/SEG11 Pin V SS Schmitt Trigger Q1 DS41265A-page 51 ...
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... PIC16F946 3.4.1.6 RC5/T1CKI/CCP1/SEG10 Figure 3-19 shows the diagram for this pin. The RC5/T1CKI/CCP1/SEG10 pin is configurable to function as one of the following: • a general purpose I/O • a TMR1 clock input • a Capture input, Compare output or PWM output • an analog output for the LCD FIGURE 3-19: ...
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... If all three data output sources are enabled, the following priority order will be used: • USART data • SSP data • PORT data © 2005 Microchip Technology Inc. ( SE9 and LCDEN SE9 and LCDEN Preliminary PIC16F946 V DD RC6/TX/ CK/SCK/ SCL/SEG9 V SS Pin Schmitt Trigger DS41265A-page 53 ...
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... PIC16F946 3.4.1.8 RC7/RX/DT/SDI/SDA/SEG8 Figure 3-21 shows the diagram for this pin. The RC7/RX/DT/SDI/SDA/SEG8 pin is configurable to function as one of the following: • a general purpose I/O • an asynchronous serial input • a synchronous serial data I/O • a SPI data I/O 2 • data I/O • an analog output for the LCD ...
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... TRISC3 TRISC2 WERR VLCDEN CS1 CS0 SE5 SE4 SE3 SE2 SE13 SE12 SE11 SE10 Preliminary PIC16F946 Value on all Value on: Bit 1 Bit 0 other POR, BOR Resets RC1 RC0 xxxx xxxx uuuu uuuu TMR1CS TMR1ON 0000 0000 uuuu uuuu SSPM1 SSPM0 0000 0000 0000 0000 ...
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... PORTD and TRISD Registers PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configured as an input or output. PORTD is only available on the PIC16F946 and PIC16F946. Note: Analog lines that carry LCD signals (i.e., SEGx, COMy, where x and y are seg- ment and common identifiers) are shown as direct connections to the device pins ...
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... I/O • an analog output for the LCD 3.5.1.8 RD7/SEG20 Figure 3-25 shows the diagram for this pin. The RD7/SEG20 pin is configurable to function as one of the following: • a general purpose I/O • an analog output for the LCD Preliminary PIC16F946 DS41265A-page 57 ...
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... PIC16F946 FIGURE 3-22: BLOCK DIAGRAM OF RD0/COM3 Data Bus PORTD CK Q Data Latch TRISD CK Q TRIS Latch RD TRISD RD PORTD COM3 FIGURE 3-23: BLOCK DIAGRAM OF RD1 Data Bus PORTD CK Q Data Latch TRISD CK Q TRIS Latch RD TRISD RD PORTD DS41265A-page 58 Schmitt Trigger LCDEN and LMUX<1:0> LCDEN and LMUX< ...
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... FIGURE 3-25: BLOCK DIAGRAM OF RD<7:3> Data Bus PORTD CK Q Data Latch TRISD CK Q TRIS Latch RD TRISD RD PORTD SE<20:16> and LCDEN SEG<20:16> © 2005 Microchip Technology Inc Schmitt Trigger SE<20:16> and LCDEN Schmitt Trigger Preliminary PIC16F946 V DD RD2/CCP2 Pin V DD RD<7:3> Pin DS41265A-page 59 ...
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... PIC16F946 TABLE 3-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Address Name Bit 7 Bit 6 08h PORTD RD7 RD6 (2) 1Dh CCP2CON — — 88h TRISD TRISD7 TRISD6 107h LCDCON LCDEN SLPEN (1) 11Eh LCDSE2 SE23 SE22 Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTD. ...
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... Bit is cleared R/W-1 R/W-1 R-1 TRISE5 TRISE4 TRISE3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F946 INITIALIZING PORTE ;Bank 0 ; ;Init PORTE ;Bank 1 ; ;Set RE<3:0> as inputs ; ;Make RE<2:0> as I/O’s ;Bank 0 ; ...
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... PIC16F946 3.6.1 PIN DESCRIPTIONS AND DIAGRAMS Each PORTE pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the comparator or the A/D, refer to the appropriate section in this data sheet. ...
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... CK Q Data Latch TRISE CK Q TRIS Latch RD TRISE RD PORTE SEG<27:21> (1) AN<7:5> Note 1: Analog input for A/D apply to RE<2:0> pins only. © 2005 Microchip Technology Inc. Analog Mode or Schmitt SE<27:21> and LCDEN Trigger SE<27:21> and LCDEN Preliminary PIC16F946 V DD RE<7:4,2:0> Pins DS41265A-page 63 ...
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... PIC16F946 FIGURE 3-27: BLOCK DIAGRAM OF RE3/MCLR/V MCLR circuit Programming mode Data Bus RE TRISE RE PORTE Note 1: RE3 will read ‘0’ when pin is MCLR. TABLE 3-5: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Address Name Bit 7 Bit 6 09h PORTE RE7 R6 1Fh ADCON0 ADFM VCFG1 ...
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... Bit is cleared R/W-1 R/W-1 R/W-1 TRISF5 TRISF4 TRISF3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F946 INITIALIZING PORTF ;Bank 3 ; ;Init PORTF ;Bank 1 ; ;Set RF<3:0> as inputs ; ;Make RF<2:0> as I/O’s ;Bank 0 ; ...
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... PIC16F946 3.7.1 PIN DESCRIPTIONS AND DIAGRAMS Each PORTF pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions, refer to the appropriate section in this data sheet. 3.7.1.1 RF0/SEG32 Figure 3-28 shows the diagram for this pin. The ...
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... TRISF5 TRISF4 TRISF3 TRISF2 RF5 RF4 RF3 RF2 SE29 SE28 SE27 SE26 SE37 SE36 SE35 SE34 Preliminary PIC16F946 V DD RF<7:0> Pin Value on all Value on: Bit 1 Bit 0 other POR, BOR Resets ADON 0000 0000 0000 0000 ANS1 ANS0 1111 1111 1111 1111 ...
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... PIC16F946 3.8 PORTG and TRISG Registers PORTG is an 8-bit port with Schmitt Trigger input buffers. RG<5:0> are individually configured as inputs or outputs, depending on the state of the port direction. The port bits are also multiplexed with LCD segment functions. Note: Analog lines that carry LCD signals (i ...
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... LCD 3.8.1.6 RG5/SEG41 Figure 3-29 shows the diagram for this pin. The RG5/SEG41 pin is configurable to function as one of the following: • a general purpose I/O • an analog output for the LCD © 2005 Microchip Technology Inc. Preliminary PIC16F946 DS41265A-page 69 ...
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... PIC16F946 FIGURE 3-29: BLOCK DIAGRAM OF RG<5:0> Data Bus PORTG CK Q Data Latch TRISG CK Q TRIS Latch RD TRISG RD PORTG SEG<41:36> TABLE 3-7: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Address Name Bit 7 Bit 6 1Fh ADCON0 ADFM VCFG1 91h ANSEL ANS7 ANS6 107h LCDCON LCDEN ...
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... OSC2 Sleep OSC1 Internal Oscillator HFINTOSC 8 MHz LFINTOSC 31 kHz © 2005 Microchip Technology Inc. The PIC16F946 can be configured in one of eight clock modes – External clock with I/O on RA6 – Low-gain Crystal or Ceramic Resonator Oscillator mode – Medium-gain Crystal or Ceramic Resonator Oscillator mode. ...
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... PIC16F946 REGISTER 4-1: OSCCON – OSCILLATOR CONTROL REGISTER (ADDRESS: 8Fh) U-0 R/W-1 — IRCF2 bit 7 bit 7 Unimplemented: Read as ‘0’ bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits 000 = 31 kHz 001 = 125 kHz 010 = 250 kHz 011 = 500 kHz 100 = 1 MHz ...
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... External Clock Modes 4.3.1 OSCILLATOR START-UP TIMER (OST) If the PIC16F946 is configured for LP modes, the Oscillator Start-up Timer (OST) counts 1024 oscil- lations from the OSC1 pin, following a Power-on Reset (POR), and the Power-up Timer (PWRT) has expired (if configured wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended ...
Page 76
... PIC16F946 TABLE 4-1: OSCILLATOR DELAY EXAMPLES System Clock Frequency Switching From Source LFIOSC 31 kHz HFIOSC 125 kHz-8 MHz 4-20 MHz INTOSC or Sleep LP 32 kHz INTOSC or Sleep LP with T1OSC 32 kHz enabled EC, RC 0-20 MHz EC, RC 0-20 MHz DS41265A-page 74 Oscillator Delay (T ) OST Sleep ...
Page 77
... The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC16F946 design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. ...
Page 78
... C2 Resonator Note 1: A series resistor (R ceramic resonators with low drive level. 2: The value of R mode selected (typically between additional parallel feedback resistor (R resonator operation (typical value vary Preliminary CERAMIC RESONATOR OPERATION ( MODE) PIC16F946 OSC1 To Int. Logic (2) ( Sleep OSC2 ( may be required for ...
Page 79
... The user also needs to take into account EXT variation due to tolerance of external RC components used. © 2005 Microchip Technology Inc. 4.4 Internal Clock Modes The PIC16F946 has two independent, internal oscillators that can be configured or selected as the system clock source. 1. The HFINTOSC Oscillator) is factory calibrated and operates at 8 MHz. The frequency of the HFINTOSC can be user adjusted ± ...
Page 80
... PIC16F946 4.4.2.1 OSCTUNE Register The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 4-2). The OSCTUNE register has a tuning range of ±12%. The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. Due to process variation, the monotonicity and frequency step cannot be specified ...
Page 81
... IRCF bits. After a Reset, SCS is always cleared. Note: Any automatic clock switch, which may occur from Fail-Safe Clock Monitor, does not update the SCS bit. The user can monitor the OSTS (OSCCON<3>) to determine the current system clock source. Preliminary PIC16F946 Two-Speed Start-up or DS41265A-page 79 ...
Page 82
... Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit (OSCCON<3>) to remain clear. When the PIC16F946 is configured for LP modes, the Oscillator Start-up Timer (OST) is enabled (see Section 4.3.1 “Oscillator Start-up (OST)” ...
Page 83
... Failure Detected failure has been detected. The assigned internal oscillator is enabled when FSCM is enabled as reflected by the IRCF. Note 1: Two-Speed 2: Primary clocks with a frequency Preliminary PIC16F946 Start-up is automatically enabled when the Fail-Safe Clock Monitor mode is enabled ...
Page 84
... The Fail-Safe condition is cleared after a Reset, the execution of a SLEEP instruction modification of the SCS bit. While in Fail-Safe condition, the PIC16F946 uses the internal oscillator as the system without exiting the Fail-Safe condition. The Fail-Safe condition must be cleared before the OSFIF flag can be cleared. ...
Page 85
... Interrupt Service Routine before re-enabling this interrupt. The Timer0 interrupt cannot wake the processor from Sleep, since the timer is shut off during Sleep. 8-bit Prescaler PSA 8 PS<2:0> 16-bit 16 PSA WDTPS<3:0> Preliminary PIC16F946 Data Bus 8 1 SYNC 2 TMR0 Cycles 0 Set Flag bit T0IF on Overflow 1 WDT Time-out 0 ...
Page 86
... Bit Value TMR0 Rate WDT Rate 000 001 010 011 100 101 110 111 Note 1: A dedicated 16-bit WDT postscaler is available for the PIC16F946. See Section 16.6 “Watchdog Timer (WDT)” for more information. Legend Readable bit - n = Value at POR DS41265A-page 84 R/W-1 R/W-1 R/W-1 ...
Page 87
... T0IE INTE RBIE T0IF INTF T0CS T0SE PSA PS2 PS1 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 Preliminary PIC16F946 CHANGING PRESCALER (TIMER0 WDT) ;Bank 0 ;Clear WDT ;Clear TMR0 and ; prescaler ;Bank 1 ;Required if desired ; PS2:PS0 is ; 000 or 001 ; ;Set postscaler to ; desired WDT rate ;Bank 0 CHANGING PRESCALER ...
Page 88
... PIC16F946 NOTES: DS41265A-page 86 Preliminary © 2005 Microchip Technology Inc. ...
Page 89
... TIMER1 MODULE WITH GATE CONTROL The PIC16F946 has a 16-bit timer. Figure 6-1 shows the basic block diagram of the Timer1 module. Timer1 has the following features: • 16-bit timer/counter (TMR1H:TMR1L) • Readable and writable • Internal or external clock selection • Synchronous or asynchronous operation • ...
Page 90
... PIC16F946 6.1 Timer1 Modes of Operation Timer1 can operate in one of three modes: • 16-bit timer with prescaler • 16-bit synchronous counter • 16-bit asynchronous counter In Timer mode, Timer1 is incremented on every instruction cycle. In Counter mode, Timer1 is incremented on the rising edge of the external clock input T1CKI. In addition, the Counter mode clock can be synchronized to the microcontroller system clock or run asynchronously ...
Page 91
... Value at POR © 2005 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 T1CKPS1 T1CKPS0 T1OSCEN (1) (2) /4) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F946 R/W-0 R/W-0 R/W-0 T1SYNC TMR1CS TMR1ON bit Bit is unknown DS41265A-page 89 ...
Page 92
... PIC16F946 6.5 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt-on-overflow, which will wake-up the processor ...
Page 93
... TXIF SSPIF CCP1IF TMR2IF — — — — T1GSS TXIE SSPIE CCP1IE TMR2IE Preliminary PIC16F946 Value on Value on Bit 1 Bit 0 all other POR, BOR Resets INTF RBIF 0000 000x 0000 000x TMR1IF 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu ...
Page 94
... PIC16F946 NOTES: DS41265A-page 92 Preliminary © 2005 Microchip Technology Inc. ...
Page 95
... TMR2 is not cleared when T2CON is written. R/W-0 R/W-0 R/W-0 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F946 /4) has a prescale option OSC ) h R/W-0 R/W-0 R/W-0 bit Bit is unknown DS41265A-page 93 ...
Page 96
... PIC16F946 7.2 Timer2 Interrupt The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset. FIGURE 7-1: ...
Page 97
... RA3/AN3/C1+/V +/SEG15 REF - connects to RA0/AN0/C1-/SEG12 + connects to internal 0.6V reference + connects to RA2/AN2/C2+/V -/COM2 REF ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F946 R/W-0 R/W-0 R/W-0 CM2 CM1 CM0 bit Bit is unknown DS41265A-page 95 ...
Page 98
... PIC16F946 8.1 Comparator Operation A single comparator is shown in Figure 8-1 along with the relationship between the analog input levels and the digital output. When the analog input at V than the analog input V -, the output of the comparator digital low level. When the analog input at V ...
Page 99
... RA0/AN0/ A C1-/SEG12 Off (Read as ‘0’) A RA3/AN3/ C1+/V +/SEG15 REF RA1/AN1/ A C2-/SEG7 C2OUT A RA2/AN2/ C2+/V -/COM2 REF RA5 D = Digital Input. CIS (CMCON0<3>) is the computer Input Switch. Preliminary PIC16F946 Off (Read as ‘0’ Off (Read as ‘0’ CIS = CIS = 1 C1OUT ...
Page 100
... PIC16F946 FIGURE 8-4: COMPARATOR C1 OUTPUT BLOCK DIAGRAM To C1OUT pin To Data Bus RD CMCON Set C1IF bit FIGURE 8-5: COMPARATOR C2 OUTPUT BLOCK DIAGRAM C2SYNC To TMR1 To C2OUT pin To Data Bus RD CMCON Set C2IF bit Note 1: Comparator 2 output is latched on falling edge of T1 clock source. DS41265A-page 98 ...
Page 101
... CxIF to be cleared. Note change in the CMCON0 register (CxOUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CxIF (PIR2<6:5>) interrupt flag may not get set. Preliminary PIC16F946 U-0 R/W-1 R/W-0 — T1GSS C2SYNC bit 0 ...
Page 102
... PIC16F946 8.6 Comparator Reference The Comparator module also allows the selection of an internally generated voltage reference for one of the comparator inputs. The VRCON register, Register 8-3, controls the voltage reference module shown in Figure 8-6. 8.6.1 CONFIGURING THE VOLTAGE REFERENCE The voltage reference can output 32 distinct voltage levels ...
Page 103
... VRCON registers to their Reset states. This forces the Comparator module the Comparator Reset mode, CM<2:0> = 000 and the voltage reference to its OFF state. Thus, all potential inputs are analog inputs with the comparator and voltage reference disabled to consume the smallest current possible. Preliminary PIC16F946 DS41265A-page 101 ...
Page 104
... PIC16F946 REGISTER 8-3: VRCON – VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 9Dh) R/W-0 VREN bit 7 bit 7 VREN: CV REF circuit powered on REF circuit powered down REF bit 6 Unimplemented: Read as ‘0’ bit 5 VRR: CV Range Selection bit REF 1 = Low range 0 = High range bit 4 Unimplemented: Read as ‘0’ ...
Page 105
... LIQUID CRYSTAL DISPLAY (LCD) DRIVER MODULE The Liquid Crystal Display (LCD) driver module generates the timing control to drive a static or multiplexed LCD panel. In the PIC16F946 device, the module drives the panels four commons and segments. It also provides control of the LCD pixel data. ...
Page 106
... PIC16F946 FIGURE 9-1: LCD DRIVER MODULE BLOCK DIAGRAM Data Bus Timing Control F /8192 OSC Clock Source T10SC/32 LFINTOSC/32 Note 1: These signals are connected directly to the I/O pads, but may be tri-stated, depending on the configuration of the LCD module. DS41265A-page 104 168 LCDDATAx SEG<42:0> ...
Page 107
... Static (COM0) 42 1/2 (COM<1:0>) 84 1/3 (COM<2:0>) 126 1/4 (COM<3:0>) 168 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F946 R/W-0 R/W-1 R/W-1 CS0 LMUX1 LMUX0 bit 0 Bias Static 1/2 or 1/3 1/2 or 1/3 1/3 ...
Page 108
... PIC16F946 REGISTER 9-2: LCDPS – LCD PRESCALER SELECT REGISTER (ADDRESS: 108h) R/W-0 R/W-0 WFT BIASMD bit 7 bit 7 WFT: Waveform Type Select bit 1 = Type-B waveform (phase changes on each frame boundary Type-A waveform (phase changes within each common type) bit 6 BIASMD: Bias Mode Select bit When LMUX< ...
Page 109
... R/W-0 R/W-0 R/W-0 SEGx- SEGx- SEGx- COMy COMy COMy W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F946 R/W-0 R/W-0 R/W-0 SEn SEn SEn bit Bit is unknown R/W-0 R/W-0 R/W-0 SEGx- SEGx- SEGx- ...
Page 110
... PIC16F946 9.1 LCD Clock Source Selection The LCD driver module has 3 possible clock sources: • F /8192 OSC • T1OSC/32 • LFINTOSC/32 The first clock source is the system clock divided by 8192 (F /8192). This divider ratio is chosen to OSC provide about 1 kHz output when the system clock is 8 MHz. The divider is not programmable. Instead, the LCD prescaler bits, LCDPS< ...
Page 111
... Clock source is F LFINTOSC/32. TABLE 9-3: LP<3:0> RB5 4 5 Digital I/O 6 COM1 Driver 7 Preliminary PIC16F946 FRAME FREQUENCY FORMULAS Frame Frequency = Clock source/( (LP<3:0> + 1)) Clock source/( (LP<3:0> + 1)) Clock source/( (LP<3:0> + 1)) Clock source/( (LP<3:0> + 1)) /8192, T1OSC/32 or OSC APPROXIMATE FRAME FREQUENCY (IN Hz) USING MHz, TIMER1 @ OSC 32 ...
Page 112
... PIC16F946 FIGURE 9-3: LCD CLOCK GENERATION F OSC ÷8192 T1OSC 32 kHz ÷32 Crystal Osc. LFINTOSC ÷32 Nom kHz RC CS<1:0> (LCDCON<3:2>) DS41265A-page 110 STAT ÷4 DUP ÷2 4-bit Prog Presc TRIP QUAD LP<3:0> (LCDPS<3:0>) LMUX<1:0> (LCDCON<1:0>) Preliminary © 2005 Microchip Technology Inc. ÷ Ring Counter LMUX< ...
Page 113
... FIGURE 9-4: LCD SEGMENT MAPPING WORKSHEET (PART © 2005 Microchip Technology Inc. Preliminary PIC16F946 DS41265A-page 111 ...
Page 114
... PIC16F946 FIGURE 9-5: LCD SEGMENT MAPPING WORKSHEET (PART DS41265A-page 112 Preliminary © 2005 Microchip Technology Inc. ...
Page 115
... Sleep. Thus, take care to see that V on all pixels is ‘0’ when Sleep is executed. Figure 9-6 through Figure 9-16 provide waveforms for static, half-multiplex, quarter-multiplex drives for Type-A and Type-B waveforms. COM0 SEG0 SEG1 1 Frame Preliminary PIC16F946 DC on all the pixels is DC /8192, OSC DC one-third-multiplex and ...
Page 116
... PIC16F946 FIGURE 9-7: TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 DS41265A-page 114 COM0 COM1 SEG0 SEG1 1 Frame Preliminary © 2005 Microchip Technology Inc. ...
Page 117
... FIGURE 9-8: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 © 2005 Microchip Technology Inc. COM0 COM1 SEG0 SEG1 2 Frames Preliminary PIC16F946 DS41265A-page 115 ...
Page 118
... PIC16F946 FIGURE 9-9: TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 DS41265A-page 116 COM0 COM1 SEG0 SEG1 1 Frame Preliminary © 2005 Microchip Technology Inc. ...
Page 119
... FIGURE 9-10: TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 © 2005 Microchip Technology Inc. COM0 COM1 SEG0 SEG1 2 Frames Preliminary PIC16F946 DS41265A-page 117 ...
Page 120
... PIC16F946 FIGURE 9-11: TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 DS41265A-page 118 COM0 COM1 COM2 SEG0 SEG2 SEG1 Preliminary Frame © 2005 Microchip Technology Inc. ...
Page 121
... FIGURE 9-12: TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 © 2005 Microchip Technology Inc. COM0 COM1 COM2 SEG0 SEG1 Preliminary PIC16F946 Frames DS41265A-page 119 ...
Page 122
... PIC16F946 FIGURE 9-13: TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 DS41265A-page 120 COM0 COM1 COM2 SEG0 SEG2 SEG1 Preliminary Frame © 2005 Microchip Technology Inc. ...
Page 123
... FIGURE 9-14: TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 © 2005 Microchip Technology Inc. COM0 COM1 COM2 SEG0 SEG1 Preliminary PIC16F946 Frames DS41265A-page 121 ...
Page 124
... PIC16F946 FIGURE 9-15: TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 DS41265A-page 122 COM0 COM1 COM2 COM3 SEG0 SEG1 1 Frame Preliminary © 2005 Microchip Technology Inc. ...
Page 125
... FIGURE 9-16: TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 © 2005 Microchip Technology Inc. COM0 COM1 COM2 COM3 SEG0 SEG1 2 Frames Preliminary PIC16F946 DS41265A-page 123 ...
Page 126
... PIC16F946 9.8 LCD Interrupts The LCD timing generation provides an interrupt that defines the LCD frame timing. This interrupt can be used to coordinate the writing of the pixel data with the start of a new frame. Writing pixel data at the frame boundary allows a visually crisp transition of the image. ...
Page 127
... TABLE 9-4: LCD MODULE STATUS DURING SLEEP Clock Source SLPEN During Sleep? 0 T1OSC 1 0 LFINTOSC OSC 1 Note: The LFINTOSC or external T1OSC oscillator must be used to operate the LCD module during Sleep. © 2005 Microchip Technology Inc. Operation Yes No Yes Preliminary PIC16F946 DS41265A-page 125 ...
Page 128
... PIC16F946 FIGURE 9-18: SLEEP ENTRY/EXIT WHEN SLPEN = 1 OR CS<1:0> COM0 COM1 COM2 SEG0 2 Frames SLEEP Instruction Execution DS41265A-page 126 Wake-up Preliminary © 2005 Microchip Technology Inc ...
Page 129
... LCDDATA0 through LCDDATA11. 5. Clear LCD Interrupt Flag, LCDIF (PIR2<4>) and if desired, enable the interrupt by setting bit LCDIE (PIE2<4>). 6. Enable bias voltage pins (VLCD<3:1>) by setting VLCDEN (LCDCON<4>). 7. Enable the LCD module by setting bit LCDEN (LCDCON<7>). © 2005 Microchip Technology Inc. Preliminary PIC16F946 DS41265A-page 127 ...
Page 130
... PIC16F946 TABLE 9-5: REGISTERS ASSOCIATED WITH LCD OPERATION Address Name Bit 7 Bit 6 10h T1CON T1GINV T1GE 0Bh/8Bh/ INTCON GIE PEIE 10Bh/18Bh 0Dh PIR2 OSFIF C2IF 8Dh PIE2 OSFIE C2IE 107h LCDCON LCDEN SLPEN 108h LCDPS WFT BIASMD 110h LCDDATA0 SEG7 SEG6 ...
Page 131
... SEG41 COM3 SE29 SE28 SE27 SE26 SE25 SE37 SE36 SE35 SE34 SE33 — — — — SE41 Preliminary PIC16F946 Value on Value on Bit 0 all other POR, BOR Resets SEG24 xxxx xxxx uuuu uuuu COM3 SEG32 xxxx xxxx uuuu uuuu COM3 SEG40 ---- --xx ---- --uu ...
Page 132
... PIC16F946 NOTES: DS41265A-page 130 Preliminary © 2005 Microchip Technology Inc. ...
Page 133
... The voltage detection monitors the internal power supply. 10.1 Voltage Trip Points The PIC16F946 device supports eight internal PLVD trip points. See Register 10-1 for available PLVD trip point voltages. REGISTER 10-1: LVDCON – LOW-VOLTAGE DETECT CONTROL REGISTER (ADDRESS: 109h) U-0 — ...
Page 134
... PIC16F946 TABLE 10-1: REGISTERS ASSOCIATED WITH PROGRAMMABLE LOW-VOLTAGE DETECT Address Name Bit 7 Bit 6 0Bh/8Bh/ INTCON GIE PEIE 10Bh/18Bh 0Dh PIR2 OSFIF C2IF 8Dh PIE2 OSFIE C2IE 109h LVDCON — — Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the PLVD module. ...
Page 135
... R/W-0 R/W-0 R/W-0 U-0 TX9 TXEN SYNC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F946 R/W-0 R-1 R/W-0 — BRGH TRMT TX9D bit Bit is unknown DS41265A-page 133 ...
Page 136
... PIC16F946 REGISTER 11-2: RCSTA – RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h) R/W-0 R/W-0 SPEN bit 7 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RC7/RX/DT/SDI/SDA/SEG8 and RC6/TX/CK/SCK/SCL/SEG9 pins as serial port pins Serial port disabled bit 6 RX9: 9-bit Receive Enable bit ...
Page 137
... Bit 4 Bit 3 Bit 2 Bit 1 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x Preliminary PIC16F946 /( 1)) equation can reduce the OSC BRGH = 1 (High Speed) /( 1)) OSC N/A Value on Value on: Bit 0 all other ...
Page 138
... PIC16F946 TABLE 11-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = MHz OSC BAUD SPBRG RATE % value (K) KBAUD ERROR KBAUD (decimal) 0.3 — — — 1.2 1.221 1.75 255 2.4 2.404 0.17 129 9.6 9.766 1.73 31 19.2 19.531 1.72 15 19.231 28.8 31.250 8. ...
Page 139
... TXIF 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Load data to the TXREG register (starts transmission using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. Preliminary PIC16F946 pin will revert to DS41265A-page 137 ...
Page 140
... PIC16F946 FIGURE 11-1: USART TRANSMIT BLOCK DIAGRAM TXIF TXIE MSb (8) Interrupt TXEN Baud Rate CLK SPBRG Baud Rate Generator FIGURE 11-2: ASYNCHRONOUS MASTER TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) RC6/TX/CK/ Start bit SCK/SCL/SEG9 TXIF bit (Transmit Buffer Reg. Empty Flag) ...
Page 141
... TMR2IF SREN CREN ADDEN FERR OERR RCIE TXIE SSPIE CCP1IE TMR2IE TXEN SYNC — BRGH TRMT Preliminary PIC16F946 Value on Value on: Bit 0 all other POR, BOR Resets RBIF 0000 000x 0000 000x TMR1IF 0000 0000 0000 0000 RX9D 0000 000x 0000 000x ...
Page 142
... PIC16F946 11.2.2 USART ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 11-4. The data is received RC7/RX/DT/SDI/SDA/SEG8 pin and drives the data recovery block. The data recovery block is actually a high-speed shifter, operating at x16 times the baud rate; whereas the main receive serial shifter operates at the bit rate ...
Page 143
... SSPIF CCP1IF TMR2IF TMR1IF SREN CREN ADDEN FERR OERR RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE TXEN SYNC — BRGH TRMT Preliminary PIC16F946 FERR RSR Register LSb Start 1 0 RCREG Register FIFO 8 Data Bus Start bit Stop Stop bit 7/8 bit bit ...
Page 144
... PIC16F946 11.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT When setting up an Asynchronous Reception with address detect enabled: • Initialize the SPBRG register for the appropriate baud rate high-speed baud rate is desired, set bit BRGH. • Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. • ...
Page 145
... CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 SREN CREN ADDEN FERR OERR RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 TXEN SYNC — BRGH TRMT Preliminary PIC16F946 Stop bit Word 1 RCREG Stop bit Word 1 RCREG Value on Value on: Bit 0 all other POR, BOR Resets ...
Page 146
... PIC16F946 11.3 USART Synchronous Master Mode In Synchronous Master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit, SYNC (TXSTA<4>). In addition, enable bit, SPEN (RCSTA<7>), is set in order ...
Page 147
... CCP1IE TMR2IE TMR1IE 0000 0000 TXEN SYNC — BRGH TRMT Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 bit 1 bit 2 bit 7 bit 0 Word 1 bit 0 bit 2 bit 1 Preliminary PIC16F946 Value on Value on: Bit 0 all other POR, BOR Resets RBIF 0000 000x 0000 000x 0000 0000 RX9D 0000 000x 0000 000x 0000 0000 0000 0000 ...
Page 148
... PIC16F946 11.3.2 USART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either enable (RCSTA<5>), or enable bit, CREN (RCSTA<4>). Data is sampled on the RC7/RX/DT/SDI/SDA/SEG8 pin on the falling edge of the clock. If enable bit SREN is set, then only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared ...
Page 149
... If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Start transmission by loading data to the TXREG register using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. Preliminary PIC16F946 Q1Q2Q3Q4 bit 5 bit 6 bit 7 ‘0’ DS41265A-page 147 ...
Page 150
... PIC16F946 TABLE 11-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Address Name Bit 7 Bit 6 0Bh, 8Bh, INTCON GIE PEIE 10Bh,18Bh 0Ch PIR1 EEIF ADIF 18h RCSTA SPEN RX9 19h TXREG USART Transmit Data Register 8Ch PIE1 EEIE ADIE 98h TXSTA CSRC TX9 ...
Page 151
... CONVERTER (A/D) MODULE The Analog-to-Digital converter (A/D) allows conversion of an analog input signal to a 10-bit binary representation of that signal. The PIC16F946 has up to eight analog inputs, multiplexed into one sample and hold circuit. The output of the sample and hold is connected to the input of the converter ...
Page 152
... Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. 12.1.2 CHANNEL SELECTION There are up to eight analog channels on the PIC16F946, AN<7:0>. The CHS<2:0> bits (ADCON0<4:2>) control which channel is connected to the sample and hold circuit. 12.1.3 ...
Page 153
... ADRESH and ADRESL registers are loaded, GO/DONE bit is cleared, ADIF bit is set, Holding Capacitor is Connected to Analog Input ADRESH bit 0 bit 7 10-bit A/D Result MSB bit 0 bit 7 10-bit A/D Result Preliminary PIC16F946 ADRESL LSB bit 0 Unimplemented: Read as ‘0’ LSB bit 0 DS41265A-page 151 ...
Page 154
... PIC16F946 REGISTER 12-1: ANSEL – ANALOG SELECT REGISTER (ADDRESS: 91h) R/W-1 R/W-1 ANS7 ANS6 bit 7 bit 7-0: ANS<7:0>: Analog Select bits Select between analog or digital function on pins AN<7:0>, respectively Analog input. Pin is assigned as analog input Digital I/O. Pin is assigned to port or special function. ...
Page 155
... Value at POR © 2005 Microchip Technology Inc. R/W-0 R/W-0 U-0 U-0 ADCS1 ADCS0 — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F946 U-0 U-0 — — — bit Bit is unknown DS41265A-page 153 ...
Page 156
... PIC16F946 12.1.7 CONFIGURING THE A/D After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as inputs. To determine sample time, see Section 19.0 “Electrical Specifications” ...
Page 157
... R ln(1/2047 10k ln(0.0004885) /° has no effect on the equation, since it cancels itself out not discharged after each conversion. HOLD Preliminary PIC16F946 the minimum acquisition time, , see ACQ ® Mid-Range MCU Family Reference + Temperature Coefficient charged to within 1/2 lsb charge response to V APPLIED ...
Page 158
... PIC16F946 FIGURE 12-4: ANALOG INPUT MODEL ANx PIN Legend Input Capacitance PIN V = Threshold Voltage Leakage current at the pin due to LEAKAGE various junctions R = Interconnect Resistance Sampling Switch C = Sample/Hold Capacitance (from DAC) HOLD 12.3 A/D Operation During Sleep The A/D converter module can operate during Sleep. ...
Page 159
... TRISA1 TRISE4 TRISE3 TRISE2 TRISE1 RCIE TXIE SSPIE CCP1IE TMR2IE ANS4 ANS3 ANS2 ADCS0 — — Preliminary PIC16F946 Value on Value on: Bit 1 Bit 0 all other POR, BOR Resets RA1 RA0 xxxx xxxx uuuu uuuu RE1 RE0 xxxx xxxx uuuu uuuu INTF RBIF ...
Page 160
... PIC16F946 NOTES: DS41265A-page 158 Preliminary © 2005 Microchip Technology Inc. ...
Page 161
... EEDATL and EEADRL registers. Interrupt flag bit EEIF (PIR1<7>), is set when write is complete. It must be cleared in the software. EECON2 is not a physical register. Reading EECON2 will read all ‘0’s. The EECON2 register is used exclusively in the data EEPROM write sequence. Preliminary PIC16F946 DS41265A-page 159 ...
Page 162
... PIC16F946 REGISTER 13-1: EEDATL – EEPROM DATA LOW BYTE REGISTER (ADDRESS: 10Ch) R/W-0 R/W-0 EEDATL7 EEDATL6 bit 7 bit 7-0 EEDATL<7:0>: Byte value to Write to or Read from data EEPROM bits or to Read from program memory Legend Readable bit - n = Value at POR REGISTER 13-2: EEADRL – ...
Page 163
... Value at POR © 2005 Microchip Technology Inc. U-0 U-0 U-0 R/W-x — — — WRERR W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F946 R/W-0 R/S-0 R/S-0 WREN WR RD bit Bit is unknown DS41265A-page 161 ...
Page 164
... PIC16F946 13.1.2 READING THE DATA EEPROM MEMORY To read a data memory location, the user must write the address to the EEADRL register, clear the EEPGD control bit (EECON1<7>), and then set control bit RD (EECON1<0>). The data is available in the very next cycle, in the EEDATL register; therefore, it can be read in the next instruction ...
Page 165
... RD on the next ; ; Bank Byte of Program Address to read ; LS Byte of Program Address to read ; Bank 3 ; Point to PROGRAM memory ; EE Read ; Any instructions here are ignored as program ; memory is read in second cycle after BSF EECON1,RD ; Bank Byte of Program EEDATA ; ; Byte of Program EEDATA ; Preliminary PIC16F946 DS41265A-page 163 ...
Page 166
... PIC16F946 FIGURE 13-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Flash ADDR Flash Data INSTR (PC) INSTR( BSF EECON1,RD executed here executed here RD bit EEDATH EEDATL register EERHLT TABLE 13-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM Addr Name Bit 7 Bit 6 0Bh/8Bh/ INTCON GIE PEIE ...
Page 167
... Slave mode (SCK is the clock input) • Clock Polarity (Idle state of SCK) • Clock edge (output data on rising/falling edge of SCK) • Clock Rate (Master mode only) • Slave Select mode (Slave mode only) © 2005 Microchip Technology Inc. ® ® Preliminary PIC16F946 DS41265A-page 165 ...
Page 168
... PIC16F946 REGISTER 14-1: SSPSTAT – SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h) R/W-0 R/W-0 SMP bit 7 bit 7 SMP: SPI™ Data Input Sample Phase bit SPI Master mode Input data sampled at end of data output time 0 = Input data sampled at middle of data output time (Microwire) ...
Page 169
... Microchip Technology Inc. R/W-0 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 SSPM2 /4 OSC /16 OSC /64 OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F946 R/W-0 R/W-0 SSPM1 SSPM0 bit Bit is unknown DS41265A-page 167 ...
Page 170
... OE signal from the SSP module into PORTC controls the state that is read back from the TRISC<4> bit (see Section 19.4 PIC16F946-I (Industrial), PIC16F946-E (Extended)” for information on PORTC). If read-modify-write instructions, such as BSF, are performed on the TRISC register while the SS pin is high, this will cause the TRISC< ...
Page 171
... Example 14-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the SSP Status register (SSPSTAT) indicates the various status conditions. Preliminary PIC16F946 DS41265A-page 169 ...
Page 172
... PIC16F946 14.3 Enabling SPI I/O To enable the serial port, SSP Enable bit, SSPEN (SSPCON<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins ...
Page 173
... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit 5 bit 4 bit 2 bit 1 bit 3 bit 5 bit 4 bit 2 bit 1 bit 3 Preliminary PIC16F946 ) Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2 DS41265A-page 171 ...
Page 174
... PIC16F946 14.6 Slave Mode In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications ...
Page 175
... Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF © 2005 Microchip Technology Inc. bit 6 bit 5 bit 4 bit 2 bit 3 bit 6 bit 2 bit 5 bit 4 bit 3 Preliminary PIC16F946 bit 1 bit 0 bit 0 Next Q4 Cycle after Q2 bit 1 bit 0 bit 0 Next Q4 Cycle after Q2 DS41265A-page 173 ...
Page 176
... PIC16F946 14.8 Sleep Operation In Master mode, all module clocks are halted and the transmission/reception will remain in that state until the device wakes from Sleep. After the device returns to normal mode, the module will continue to trans- mit/receive data. In Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device ...
Page 177
... The SCL clock input must have a minimum high and low for proper operation. For high and low times of the I specification, as well as the requirements of the SSP module, see Section 19.0 “Electrical Specifications”. Preliminary PIC16F946 modes to be selected mode with the SSPEN bit set 2 C module ...
Page 178
... PIC16F946 14.12.1 ADDRESSING Once the SSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register ...
Page 179
... SSPIF (PIR1<3>) BF (SSPSTAT<0>) SSPOV (SSPCON<6>) © 2005 Microchip Technology Inc. Receiving Data ACK ACK Cleared in software SSPBUF register is read Bit SSPOV is set because the SSPBUF register is still full. Preliminary PIC16F946 Receiving Data ACK Bus Master terminates transfer ACK is not sent. DS41265A-page 177 ...
Page 180
... PIC16F946 2 FIGURE 14-9: I C™ SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS) DS41265A-page 178 Preliminary © 2005 Microchip Technology Inc. ...
Page 181
... A2 A1 ACK SCL held low while CPU responds to SSPIF Cleared in software SSPBUF is written in software Set bit after writing to SSPBUF (the SSPBUF must be written to before the CKP bit can be set) Preliminary PIC16F946 Transmitting Data ACK From SSP Interrupt Service Routine DS41265A-page 179 ...
Page 182
... PIC16F946 2 I FIGURE 14-11: C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) DS41265A-page 180 Preliminary © 2005 Microchip Technology Inc. ...
Page 183
... SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 14-12). Preliminary PIC16F946 2 C DS41265A-page 181 ...
Page 184
... PIC16F946 FIGURE 14-12: CLOCK SYNCHRONIZATION TIMING SDA DX SCL CKP WR SSPCON TABLE 14-4: REGISTERS ASSOCIATED WITH I Address Name Bit 7 Bit 6 0Bh, 8Bh, INTCON GIE PEIE 10Bh,18Bh 0Ch PIR1 EEIF ADIF 8Ch PIE1 EEIE ADIE 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register ...
Page 185
... Mid-Range MCU Family Reference Manual” (DS33023) and in Application Note AN594, “Using the CCP Modules” (DS00594). TABLE 15-1: CCP MODE – TIMER RESOURCES REQUIRED CCP Mode Capture Compare PWM Interaction Preliminary PIC16F946 Timer Resource Timer1 Timer1 Timer2 DS41265A-page 183 ...
Page 186
... PIC16F946 REGISTER 15-1: CCP1CON – CCP2CON U-0 — bit 7 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 CCPxX:CCPxY: PWM Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. ...
Page 187
... EXAMPLE 15-1: CLRF CCP1CON MOVLW NEW_CAPT_PS ; Load the W reg with MOVWF CCP1CON CCPR1L TMR1L Preliminary PIC16F946 CHANGING BETWEEN CAPTURE PRESCALERS ; Turn CCP module off ; the new prescaler ; move value and CCP ON ; Load CCP1CON with this ; value DS41265A-page 185 ...
Page 188
... PIC16F946 15.2 Compare Mode In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match RC5/T1CKI/CCP1/SEG10 pin is: • Driven high • Driven low • Remains unchanged The action on the pin is based on the value of control bits CCP1M<3:0> (CCP1CON<3:0>). At the same time, interrupt flag bit CCP1IF is set ...
Page 189
... The maximum PWM resolution (bits) for a given PWM frequency is given by the formula: PWM Resolution Note: If the PWM duty cycle value is longer than • OSC the RC5/T1CKI/CCP1/SEG10 pin will not be cleared. Preliminary PIC16F946 ⎛ ⎞ F OSC ------------------------------------------------------------- log ⎝ ⎠ F TMR2 Prescaler PWM ...
Page 190
... PIC16F946 15.3.3 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. Set the PWM period by writing to the PR2 register. 2. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. 3. Make the RC5/T1CKI/CCP1/SEG10 pin an output by clearing the TRISC< ...
Page 191
... TXIE SSPIE CCP1IE TMR2IE C1IE LCDIE — LVDIE CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 Preliminary PIC16F946 Value on: Value on Bit 1 Bit 0 POR, all other BOR Resets INTF RBIF 0000 000x 0000 000x TMR1IF 0000 0000 0000 0000 — ...
Page 192
... PIC16F946 NOTES: DS41265A-page 190 Preliminary © 2005 Microchip Technology Inc. ...
Page 193
... SPECIAL FEATURES OF THE CPU The PIC16F946 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving features and offer code protection. These features are: • Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) • ...
Page 194
... PIC16F946 16.1 Configuration Bits The configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’) to select various device configurations as shown in Register 16-1. These bits are mapped in program memory location 2007h. REGISTER 16-1: CONFIG – CONFIGURATION WORD (ADDRESS: 2007h) — ...
Page 195
... Reset The PIC16F946 differentiates between various kinds of Reset: a) Power-on Reset (POR) b) WDT Reset during normal operation c) WDT Reset during Sleep d) MCLR Reset during normal operation e) MCLR Reset during Sleep f) Brown-out Reset (BOR) Some registers are not affected in any Reset condition; ...
Page 196
... For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00607). 16.3.1 MCLR PIC16F946 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. ...
Page 197
... Brown-out Reset and the Power-up Timer will be re-initialized. Once V rises above V , the Power-up Timer will execute a BOR 64 ms Reset. ( & Preliminary PIC16F946 slew rate. A Reset is DD falls below V for less BOR rises above DD while the Power-up Timer BOR V BOR ...
Page 198
... Then, bringing MCLR high will begin execution immediately (see Figure 16-5). This is useful for testing purposes or to synchronize more than one PIC16F946 device operating in parallel. Table 16-5 shows the Reset conditions for some special registers, while Table 16-5 shows the Reset conditions for all the registers ...
Page 199
... Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 16-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR Internal POR PWRT Time-out OST Time-out Internal Reset © 2005 Microchip Technology Inc. T PWRT T OST T PWRT T OST DD T PWRT T OST Preliminary PIC16F946 ): CASE 3 DS41265A-page 197 ...
Page 200
... PIC16F946 TABLE 16-4: INITIALIZATION CONDITION FOR REGISTERS Power-on Register Address Reset W — xxxx xxxx INDF 00h/80h/ xxxx xxxx 100h/180h TMR0 01h/101h xxxx xxxx PCL 02h/82h/ 0000 0000 102h/182h STATUS 03h/83h/ 0001 1xxx 103h/183h FSR 04h/84h/ xxxx xxxx 104h/184h PORTA 05h xxxx xxxx ...