PIC16LC73A-04I/SO Microchip Technology, PIC16LC73A-04I/SO Datasheet - Page 80

• Manufacturer Part Number: PIC16LC73A-04I/SO
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC73A-04I/SO

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 6 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: PIC16LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 192 B
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2.5 V to 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 5 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC16LC73A-04I/SOR; PIC16LC73A-04I/SOR

PIC16C7X
11.2.1
The SPI mode allows 8-bits of data to be synchro-
nously transmitted and received simultaneously. To
accomplish communication, typically three pins are
used:
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Serial Clock (SCK)
Additionally a fourth pin may be used when in a slave
mode of operation:
• Slave Select (SS)
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>).
These control bits allow the following to be specified:
• Master Mode (SCK is the clock output)
• Slave Mode (SCK is the clock input)
• Clock Polarity (Output/Input data on the Rising/
• Clock Rate (Master mode only)
• Slave Select Mode (Slave mode only)
The SSP consists of a transmit/receive Shift Register
(SSPSR) and a Buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8-bits of data
have been received, that byte is moved to the SSPBUF
register. Then the Buffer Full bit, BF (SSPSTAT<0>)
and flag bit SSPIF are set. This double buffering of the
received data (SSPBUF) allows the next byte to start
reception before reading the data that was just
received. Any write to the SSPBUF register during
transmission/reception of data will be ignored, and the
write collision detect bit, WCOL (SSPCON<7>) will be
set. User software must clear bit WCOL so that it can
be determined if the following write(s) to the SSPBUF
completed successfully. When the application software
is expecting to receive valid data, the SSPBUF register
should be read before the next byte of data to transfer
is written to the SSPBUF register. The Buffer Full bit BF
(SSPSTAT<0>) indicates when the SSPBUF register
has been loaded with the received data (transmission
is complete). When the SSPBUF is read, bit BF is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally the SSP Interrupt is used to
determine when the transmission/reception has com-
pleted. The SSPBUF register must be read and/or writ-
ten. If the interrupt method is not going to be used, then
software polling can be done to ensure that a write col-
lision does not occur. Example 11-1 shows the loading
of the SSPBUF (SSPSR) register for data transmission.
The shaded instruction is only required if the received
data is meaningful.
DS30390E-page 80
Falling edge of SCK)
OPERATION OF SSP MODULE IN SPI
MODE
Applicable Devices
72 73 73A 74 74A 76 77
72 73 73A 74 74A 76 77
Applicable Devices
EXAMPLE 11-1: LOADING THE SSPBUF
LOOP BTFSS SSPSTAT, BF
The block diagram of the SSP module, when in SPI
mode (Figure 11-3), shows that the SSPSR register is
not directly readable or writable, and can only be
accessed from addressing the SSPBUF register. Addi-
tionally, the SSP status register (SSPSTAT) indicates
the various status conditions.
FIGURE 11-3: SSP BLOCK DIAGRAM
RC4/SDI/SDA
RC5/SDO
RA5/SS/AN4
RC3/SCK/
SCL
BSF
GOTO
BCF
MOVF
MOVWF RXDATA
MOVF
MOVWF SSPBUF
STATUS, RP0
LOOP
STATUS, RP0
SSPBUF, W
TXDATA, W
Read
SS Control
(SPI MODE)
Select
TRISC<3>
Edge
SSPM3:SSPM0
(SSPSR) REGISTER
Enable
bit0
Select
Edge
SSPBUF reg
SSPSR reg
1997 Microchip Technology Inc.
Clock Select
4
;Has data been
;Specify Bank 1
;received
;(transmit
;complete)?
;No
;Specify Bank 0
;W reg = contents
;of SSPBUF
;Save in user RAM
;W reg = contents
; of TXDATA
;New data to xmit
2
Write
Prescaler
4, 16, 64
clock
shift
TMR2 output
data bus
Internal
2
T
CY