PIC18F2550T-I/SO Microchip Technology, PIC18F2550T-I/SO Datasheet - Page 15

• Manufacturer Part Number: PIC18F2550T-I/SO
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2550T-I/SO

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, I2C, EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163025, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRD
• Lead Free Status / Rohs Status: Details

33. Module: Timer1/3
EXAMPLE 6:
34. Module: Resets (BOR)
© 2009 Microchip Technology Inc.
CLRF
MOVLW
MOVWF
For Timer1 or Timer3, if the TMRxH and TMRxL
registers are written to in consecutive instruction
cycles, the timer may not be updated with the
correct value if it is configured for externally
clocked, 8-Bit Asynchronous mode (T1CON<7:0>
or T3CON<7:0> = 0xxx x111).
For the purposes of this issue, instructions that
directly affect the contents of the Timer registers
are considered to be writes. This includes CLRF,
SETF and MOVF instructions.
Work around
Insert a delay of one or more instruction cycles
between writes to TMRxH and TMRxL. This delay
can be a NOP, or any instruction that does not
access the Timer registers (Example 6).
Affected Silicon Revisions
Certain operating conditions can move the effec-
tive Brown-out Reset (BOR) threshold outside of
the range specified in the electrical characteristics
of the Device Data Sheet (parameter D005).
The BOR threshold has been observed to increase
with high device operating frequencies, some table
read operations and heavy loading on the USB
voltage regulator. When all of these conditions are
present, BOR has been observed with V
20 percent higher than the V
for a given BORV<1:0> setting.
The BOR threshold may decrease under other
conditions, such as during Sleep, where it may not
occur until V
minimums.
Work around
None.
Affected Silicon Revisions
A3
A3
TMR1H
T1Offset
TMR1L
B4
B4
DD
X
X
TIMER1/3 – CONSECUTIVE
WRITES
is 120 mV below the specified
; 1 Tcy delay
B5
B5
X
BOR
B6
B6
X
value specified
PIC18F2455/2550/4455/4550
B7
B7
DD
35. Module: Resets (BOR)
36. Module: EUSART
37. Module: MSSP (SPI Slave)
Certain operating conditions can move the effec-
tive Brown-out Reset (BOR) threshold outside of
the range specified in the electrical characteristics
of the Device Data Sheet (parameter D005).
The BOR threshold has been observed to increase
with some table read operations. BOR has been
observed with 7 percent higher V
value specified for a given BORV<1:0> setting.
Work around
None.
Affected Silicon Revisions
In Synchronous Master mode, while transmitting
the Most Significant data bit, the data line (DT)
may change state before the bit finishes transmit-
ting. If the receiver samples the data line later than
0.5 bit times + 1.5 T
starting edge of the MSb, the bit may be read
incorrectly.
Work around
None.
Affected Silicon Revisions
If configured in SPI Slave mode, the MSSP may not
successfully recognize data packets generated by an
external master processor. This applies to all SPI
Slave modes (CKE/CKP = 1 or 0), whether or not
slave select is enabled (SSPM<3:0> = 010x).
Work around
Insert a series resistor between the SPI master
Serial Data Out (SDO) and the corresponding SPI
slave Serial Data In (SDI) input line of the
microcontroller. The required value for the resistor
varies with the application system’s characteristics
and
microcontrollers.
Experimentation
encouraged.
Affected Silicon Revisions
A3
A3
A3
the
process
B4
B4
B4
X
X
and
CY
variations
B5
B5
B5
X
X
(of the master) after the
thorough
DS80478A-page 15
DD
B6
B6
B6
X
between
than the V
testing
B7
B7
B7
X
BOR
the
are