PIC18F2682-E/SP Microchip Technology, PIC18F2682-E/SP Datasheet
PIC18F2682-E/SP
Specifications of PIC18F2682-E/SP
Related parts for PIC18F2682-E/SP
PIC18F2682-E/SP Summary of contents
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... PIC18F2682/2685/4682/4685 Enhanced Flash Microcontrollers with ECAN™ Technology, 10-Bit A/D © 2009 Microchip Technology Inc. Data Sheet 28/40/44-Pin and nanoWatt Technology DS39761C ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC18F4682 80K 40960 PIC18F4685 96K 49152 © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Peripheral Highlights: • High-Current Sink/source 25 mA/25 mA • Three External Interrupts • One Capture/Compare/PWM (CCP1) module • Enhanced Capture/Compare/PWM (ECCP1) module (40/44-pin devices only): - One, two or four PWM outputs ...
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... PIC18F2682/2685/4682/4685 Pin Diagrams 28-Pin PDIP, SOIC MCLR/V PP RA0/AN0 RA1/AN1 RA2/AN2/V RA3/AN3/V RA4/T0CKI RA5/AN4/SS/HLVDIN OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T13CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL 40-Pin PDIP MCLR/V /RE3 PP RA0/AN0/CV RA1/AN1 RA2/AN2/V REF RA3/AN3/V REF RA4/T0CKI RA5/AN4/SS/HLVDIN RE0/RD/AN5 RE1/WR/AN6/C1OUT RE2/CS/AN7/C2OUT OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T13CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RD0/PSP0/C1IN+ ...
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... Pin Diagrams (Continued) 44-Pin TQFP RC7/RX/DT RD4/PSP4/ECCP1/P1A RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D RB0/INT0/FLT0/AN10 RB1/INT1/AN8 RB2/INT2/CANTX RB3/CANRX 44-Pin QFN RC7/RX/DT RD4/PSP4/ECCP1/P1A RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D RB0/INT0/FLT0/AN10 RB1/INT1/AN8 RB2/INT2/CANTX Note: Pinouts are subject to change. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 PIC18F4682 PIC18F4685 PIC18F4682 PIC18F4685 RC0/T1OSO/T13CKI OSC2/CLKO/RA6 ...
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... Appendix E: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 467 Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 467 The Microchip Web Site ..................................................................................................................................................................... 481 Customer Change Notification Service .............................................................................................................................................. 481 Customer Support .............................................................................................................................................................................. 481 Reader Response .............................................................................................................................................................................. 482 PIC18F2682/2685/4682/4685 Product Identification System ............................................................................................................ 483 DS39761C-page 6 © 2009 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 DS39761C-page 7 ...
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... PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 8 © 2009 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F2682/2685/4682/4685 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F2682/2685/4682/4685 family offer ten different oscillator options, allowing users a wide range of choices in developing application hardware. These options include: • Four Crystal modes, using crystals or ceramic resonators • ...
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... Figure 1-1 and Figure 1-2. The devices are differentiated from each other in six ways: 1. Flash program memory (80 Kbytes for PIC18F2682/4682 devices, 96 Kbytes for PIC18F2685/4685 devices). 2. A/D channels (8 for PIC18F2682/2685 devices, 11 for PIC18F4682/4685 devices). 3. I/O ports (3 bidirectional ports and 1 input only port on PIC18F2682/2685 5 bidirectional ...
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... Stack Underflow (PWRT, OST), MCLR (optional), Programmable High/Low-Voltage Detect Programmable Brown-out Reset Instruction Set 75 Instructions; 83 with Extended Instruction Set Packages © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 PIC18F2682 PIC18F2685 DC – 40 MHz DC – 40 MHz 80K 96K 40960 49152 3328 3328 1024 1024 19 19 ...
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... PIC18F2682/2685/4682/4685 FIGURE 1-1: PIC18F2682/2685 (28-PIN) BLOCK DIAGRAM Table Pointer<21> inc/dec logic PCLATU PCLATH 21 20 PCU PCH Program Counter 31 Level Stack Address Latch STKPTR Program Memory (80/96 Kbytes) Data Latch 8 Table Latch ROM Latch Instruction Bus <16> IR Instruction Decode & Control Internal ...
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... RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. 2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Data Bus<8> Data Latch 8 8 Data Memory (3 ...
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... PIC18F2682/2685/4682/4685 TABLE 1-2: PIC18F2682/2685 PINOUT I/O DESCRIPTIONS Pin Number Pin Name Type PDIP, SOIC MCLR/V /RE3 1 PP MCLR V PP RE3 OSC1/CLKI/RA7 9 OSC1 CLKI RA7 OSC2/CLKO/RA6 10 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output DS39761C-page 14 ...
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... TABLE 1-2: PIC18F2682/2685 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Type PDIP, SOIC RA0/AN0 2 RA0 AN0 RA1/AN1 3 RA1 AN1 RA2/AN2 REF RA2 AN2 V - REF RA3/AN3 REF RA3 AN3 V + REF RA4/T0CKI 6 RA4 T0CKI RA5/AN4/SS/HLVDIN 7 RA5 AN4 SS HLVDIN RA6 RA7 Legend: TTL = TTL compatible input ...
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... PIC18F2682/2685/4682/4685 TABLE 1-2: PIC18F2682/2685 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Type PDIP, SOIC RB0/INT0/AN10 21 RB0 INT0 AN10 RB1/INT1/AN8 22 RB1 INT1 AN8 RB2/INT2/CANTX 23 RB2 INT2 CANTX RB3/CANRX 24 RB3 CANRX RB4/KBI0/AN9 25 RB4 KBI0 AN9 RB5/KBI1/PGM 26 RB5 KBI1 PGM RB6/KBI2/PGC 27 RB6 KBI2 ...
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... TABLE 1-2: PIC18F2682/2685 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Type PDIP, SOIC RC0/T1OSO/T13CKI 11 RC0 T1OSO T13CKI RC1/T1OSI 12 RC1 T1OSI RC2/CCP1 13 RC2 CCP1 RC3/SCK/SCL 14 RC3 SCK SCL RC4/SDI/SDA 15 RC4 SDI SDA RC5/SDO 16 RC5 SDO RC6/TX/CK 17 RC6 TX CK RC7/RX/DT 18 RC7 RX DT RE3 — ...
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... PIC18F2682/2685/4682/4685 TABLE 1-3: PIC18F4682/4685 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PDIP QFN MCLR/V /RE3 MCLR V PP RE3 OSC1/CLKI/RA7 13 32 OSC1 CLKI RA7 OSC2/CLKO/RA6 14 33 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output DS39761C-page 18 ...
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... RA5 AN4 SS HLVDIN RA6 RA7 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Pin Buffer Type Type TQFP PORTA is a bidirectional I/O port. 19 I/O TTL Digital I/O. I Analog Analog input 0. ...
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... PIC18F2682/2685/4682/4685 TABLE 1-3: PIC18F4682/4685 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN RB0/INT0/FLT0/AN10 33 9 RB0 INT0 FLT0 AN10 RB1/INT1/AN8 34 10 RB1 INT1 AN8 RB2/INT2/CANTX 35 11 RB2 INT2 CANTX RB3/CANRX 36 12 RB3 CANRX RB4/KBI0/AN9 37 14 RB4 KBI0 AN9 RB5/KBI1/PGM 38 15 ...
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... RC6 TX CK RC7/RX/ RC7 RX DT Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Pin Buffer Type Type TQFP PORTC is a bidirectional I/O port. 32 I/O ST Digital I/O. O — Timer1 oscillator output Timer1/Timer3 external clock input ...
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... PIC18F2682/2685/4682/4685 TABLE 1-3: PIC18F4682/4685 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN RD0/PSP0/C1IN RD0 PSP0 C1IN+ RD1/PSP1/C1IN RD1 PSP1 C1IN- RD2/PSP2/C2IN RD2 PSP2 C2IN+ RD3/PSP3/C2IN RD3 PSP3 C2IN- RD4/PSP4/ECCP1 P1A RD4 PSP4 ECCP1 P1A RD5/PSP5/P1B 28 3 RD5 PSP5 P1B ...
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... — 13 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Pin Buffer Type Type TQFP PORTE is a bidirectional I/O port. 25 I/O ST Digital I/O. I TTL Read control for Parallel Slave Port (see also WR and CS pins) ...
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... PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 24 © 2009 Microchip Technology Inc. ...
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... OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types PIC18F2682/2685/4682/4685 devices can be operated in ten different oscillator modes. The user can program the Configuration bits, FOSC3:FOSC0, in Configuration Register 1H to select one of these ten modes Low-Power Crystal 2. XT Crystal/Resonator 3. HS High-Speed Crystal/Resonator 4. HSPLL High-Speed Crystal/Resonator with PLL enabled 5 ...
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... PIC18F2682/2685/4682/4685 TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Typical Capacitor Values Crystal Tested: Osc Type Freq kHz 33 pF 200 kHz MHz MHz MHz MHz MHz 15 pF Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation ...
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... EXT C > EXT © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 2.5 PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from a crystal oscillator. This may be ...
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... PIC18F2682/2685/4682/4685 2.6 Internal Oscillator Block The PIC18F2682/2685/4682/4685 devices include an internal oscillator block which generates two different clock signals; either can be used as the microcontroller’s clock source. This may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. The main output (INTOSC MHz clock source, which can be used to directly drive the device clock ...
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... If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 R/W-0 R/W-0 R/W-0 TUN4 TUN3 TUN2 U = Unimplemented bit, read as ‘ ...
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... The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F2682/2685/4682/4685 devices are shown in Figure 2-8. See Section 24.0 “Special Features of the CPU” for Configuration register details ...
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... Timer1 oscillator starts. 2.7.2 OSCILLATOR TRANSITIONS PIC18F2682/2685/4682/4685 devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to register four cycles of the new clock source ...
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... PIC18F2682/2685/4682/4685 REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-1 R/W-0 IDLEN IRCF2 IRCF1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction ...
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... Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 a Real-Time Clock. Other features may be operating that do not require a device clock source (i.e., MSSP slave, PSP, INTx pins and others). Peripherals that may add significant current consumption are listed in Section 27.2 “ ...
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... PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 34 © 2009 Microchip Technology Inc. ...
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... POWER-MANAGED MODES PIC18F2682/2685/4682/4685 devices offer a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). There are three categories of power-managed modes: • Run modes • ...
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... PIC18F2682/2685/4682/4685 3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Three bits indicate the current clock source and its status. They are: • ...
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... RC_RUN mode is not recommended. This mode is entered by setting SCS1 to ‘1’. Although it is ignored recommended that SCS0 also be cleared; this is to maintain software compatibility with future devices. When the clock source is switched to © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 n-1 n Clock Transition ...
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... PIC18F2682/2685/4682/4685 If the IRCF bits were previously at a non-zero value or if INTSRC was set before setting SCS1 and the INTOSC source was already stable, the IOFS bit will remain set. On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTOSC multiplexer while the primary clock is started ...
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... Sleep Mode The power-managed Sleep mode in the PIC18F2682/ 2685/4682/4685 devices is identical to the legacy Sleep mode offered in all other PIC devices entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 3-5). All clock source status bits are cleared ...
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... PIC18F2682/2685/4682/4685 3.4.1 PRI_IDLE MODE This mode is unique among the three low-power Idle modes in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “ ...
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... INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section 9.0 “ ...
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... PIC18F2682/2685/4682/4685 3.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power-managed modes do not invoke the OST at all. There are two cases: • PRI_IDLE mode where the primary clock source is not stopped • The primary clock source is not any of the LP, XT HSPLL modes ...
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... RESET The PIC18F2682/2685/4682/4685 devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power-managed modes d) Watchdog Timer (WDT) Reset during execution e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset ...
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... PIC18F2682/2685/4682/4685 REGISTER 4-1: RCON: RESET CONTROL REGISTER (1) R/W-0 R/W-1 U-0 IPEN SBOREN — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) ...
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... MCLR Reset path which detects and ignores small pulses. The MCLR pin is not driven low by any internal Resets, including the WDT. In PIC18F2682/2685/4682/4685 devices, the MCLR input can be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section 10.5 “PORTE, TRISE and LATE Registers” ...
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... PIC18F2682/2685/4682/4685 4.4 Brown-out Reset (BOR) PIC18F2682/2685/4682/4685 devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV1:BORV0 BOREN1:BOREN0 Configuration bits. There are a total of four BOR configurations which are summarized in Table 4-1. The BOR threshold is set by the BORV1:BORV0 bits. If BOR is enabled (any value of BOREN1:BOREN0, except ‘ ...
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... Oscillator Start-up Timer (OST) • PLL Lock Time-out 4.5.1 POWER-UP TIMER (PWRT) The Power-up Timer (PWRT) of PIC18F2682/2685/ 4682/4685 devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 x 32 μs = 65.6 ms. ...
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... PIC18F2682/2685/4682/4685 FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
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... TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST ≈ max. First three stages of the Power-up Timer. T PLL © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 , V RISE > PWRT T OST T PWRT T OST T ...
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... PIC18F2682/2685/4682/4685 4.6 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation ...
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... PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset ...
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... PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices BSR 2682 2685 4682 4685 INDF2 2682 2685 4682 4685 POSTINC2 2682 2685 4682 4685 POSTDEC2 2682 2685 4682 4685 PREINC2 2682 2685 4682 4685 PLUSW2 2682 2685 4682 4685 ...
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... PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset ...
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... PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices PIR2 2682 2685 4682 4685 2682 2685 4682 4685 PIE2 2682 2685 4682 4685 2682 2685 4682 4685 IPR1 2682 2685 4682 4685 2682 2685 4682 4685 PIR1 2682 2685 4682 4685 ...
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... PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset ...
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... PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices RXB1SIDH 2682 2685 4682 4685 RXB1CON 2682 2685 4682 4685 TXB0D7 2682 2685 4682 4685 TXB0D6 2682 2685 4682 4685 TXB0D5 2682 2685 4682 4685 TXB0D4 2682 2685 4682 4685 ...
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... PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset ...
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... PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices RXF3SIDL 2682 2685 4682 4685 RXF3SIDH 2682 2685 4682 4685 RXF2EIDL 2682 2685 4682 4685 RXF2EIDH 2682 2685 4682 4685 RXF2SIDL 2682 2685 4682 4685 RXF2SIDH 2682 2685 4682 4685 ...
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... PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset ...
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... PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices (6) B2D1 2682 2685 4682 4685 (6) B2D0 2682 2685 4682 4685 (6) B2DLC 2682 2685 4682 4685 (6) B2EIDL 2682 2685 4682 4685 (6) B2EIDH 2682 2685 4682 4685 (6) B2SIDL 2682 2685 4682 4685 ...
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... PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset ...
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... PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices (6) RXF13EIDL 2682 2685 4682 4685 (6) RXF13EIDH 2682 2685 4682 4685 (6) RXF13SIDL 2682 2685 4682 4685 (6) RXF13SIDH 2682 2685 4682 4685 (6) RXF12EIDL 2682 2685 4682 4685 (6) RXF12EIDH 2682 2685 4682 4685 ...
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... NOP instruction). The PIC18F2682 and PIC18F4682 each have 80 Kbytes of Flash memory and can store up to 40,960 single-word instructions. The PIC18F2685 and PIC18F4685 each have 96 Kbytes of Flash memory and can store up to 49,152 single-word instructions ...
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... PIC18F2682/2685/4682/4685 5.1.1 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC< ...
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... Note 1: Bit 7 and bit 6 are cleared by user software POR. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 When the stack has been popped enough times to unload the stack, the next pop returns a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...
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... PIC18F2682/2685/4682/4685 5.1.2.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When ...
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... All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 5.2.2 INSTRUCTION FLOW/PIPELINING An “Instruction Cycle” consists of four Q cycles: Q1 through Q4 ...
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... PIC18F2682/2685/4682/4685 5.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instruc- tions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read ‘ ...
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... RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each; PIC18F2682/ 2685/4682/4685 devices implement all 16 banks. Figure 5-5 shows the data memory organization for the PIC18F2682/2685/4682/4685 devices ...
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... PIC18F2682/2685/4682/4685 FIGURE 5-5: DATA MEMORY MAP FOR PIC18F2682/2685/4682/4685 DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh 00h = 0011 Bank 3 FFh 00h = 0100 Bank 4 FFh 00h = 0101 Bank 5 FFh 00h = 0110 Bank 6 FFh 00h = 0111 Bank 7 ...
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... Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’ © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Data Memory 000h 7 00h ...
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... Table 5-1 and Table 5-2. The SFRs can be classified into two sets: those associated with the “core” device functionality (ALU, Resets and interrupts) and those related to the TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2682/2685/4682/4685 DEVICES Address Name Address FFFh TOSU ...
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... TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2682/2685/4682/4685 DEVICES (CONTINUED) Address Name Address F7Fh — F7Eh — F7Dh — F7Ch — F7Bh — F7Ah — F79h — F78h — F77h ECANCON F76h TXERRCNT F75h RXERRCNT F74h COMSTAT F73h CIOCON F72h BRGCON3 ...
Page 74
... PIC18F2682/2685/4682/4685 TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2682/2685/4682/4685 DEVICES (CONTINUED) Address Name Address EFFh — EDFh EFEh — EDEh EFDh — EDDh EFCh — EDCh EFBh — EDBh EFAh — EDAh EF9h — EF8h — EF7h — EF6h — EF5h — ...
Page 75
... TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2682/2685/4682/4685 DEVICES (CONTINUED) Address Name Address E7Fh CANCON_RO4 E7Eh CANSTAT_RO4 (2) E7Dh B5D7 (2) E7Ch B5D6 (2) E7Bh B5D5 (2) E7Ah B5D4 (2) E79h B5D3 (2) E78h B5D2 (2) E77h B5D1 (2) E76h B5D0 (2) E75h B5DLC (2) E74h B5EIDL (2) E73h B5EIDH (2) E72h B5SIDL ...
Page 76
... PIC18F2682/2685/4682/4685 TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2682/2685/4682/4685 DEVICES (CONTINUED) Address Name Address DFFh — DDFh DFEh — DDEh DFDh — DDDh DFCh TXBIE DDCh DFBh — DDBh DFAh BIE0 DDAh DF9h — DD9h DF8h BSEL0 DD8h DF7h — DD7h DF6h — ...
Page 77
... TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2682/2685/4682/4685 DEVICES (CONTINUED) Address Name D7Fh — D7Eh — D7Dh — D7Ch — D7Bh RXF11EIDL D7Ah RXF11EIDH D79h RXF11SIDL D78h RXF11SIDH D77h RXF10EIDL D76h RXF10EIDH D75h RXF10SIDL D74h RXF10SIDH D73h RXF9EIDL D72h RXF9EIDH D71h ...
Page 78
... The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. 3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685 devices; individual unimplemented bits should be interpreted as ‘—’. 4: The PLLEN bit is only available in specific oscillator configurations ...
Page 79
... The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. 3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685 devices; individual unimplemented bits should be interpreted as ‘—’. 4: The PLLEN bit is only available in specific oscillator configurations ...
Page 80
... The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. 3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685 devices; individual unimplemented bits should be interpreted as ‘—’. 4: The PLLEN bit is only available in specific oscillator configurations ...
Page 81
... The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. 3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685 devices; individual unimplemented bits should be interpreted as ‘—’. 4: The PLLEN bit is only available in specific oscillator configurations ...
Page 82
... The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. 3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685 devices; individual unimplemented bits should be interpreted as ‘—’. 4: The PLLEN bit is only available in specific oscillator configurations ...
Page 83
... The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. 3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685 devices; individual unimplemented bits should be interpreted as ‘—’. 4: The PLLEN bit is only available in specific oscillator configurations ...
Page 84
... The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. 3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685 devices; individual unimplemented bits should be interpreted as ‘—’. 4: The PLLEN bit is only available in specific oscillator configurations ...
Page 85
... The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. 3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685 devices; individual unimplemented bits should be interpreted as ‘—’. 4: The PLLEN bit is only available in specific oscillator configurations ...
Page 86
... The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. 3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685 devices; individual unimplemented bits should be interpreted as ‘—’. 4: The PLLEN bit is only available in specific oscillator configurations ...
Page 87
... The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. 3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685 devices; individual unimplemented bits should be interpreted as ‘—’. 4: The PLLEN bit is only available in specific oscillator configurations ...
Page 88
... The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. 3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685 devices; individual unimplemented bits should be interpreted as ‘—’. 4: The PLLEN bit is only available in specific oscillator configurations ...
Page 89
... For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the bits in the STATUS register ...
Page 90
... PIC18F2682/2685/4682/4685 5.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 5.6 “Data Memory and the Extended Instruction Set” for more information. While the program memory can be addressed in only one way – ...
Page 91
... ECCh will be added to that of the W register and stored back in ECCh. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 mapped in the SFR space, but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L ...
Page 92
... PIC18F2682/2685/4682/4685 5.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on its stored value. They are: • ...
Page 93
... This special addressing mode is known as Indexed Addressing with Literal Offset or Indexed Literal Offset mode. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 When using the extended instruction set, this addressing mode requires the following: • The use of the Access Bank is forced (‘a’ = 0); ...
Page 94
... PIC18F2682/2685/4682/4685 FIGURE 5-8: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF (Opcode: 0010 01da ffff ffff) When and f ≥ 60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and 0FFh ...
Page 95
... BSR. F60h FFFh © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use Direct Addressing as before. Any indirect or ...
Page 96
... PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 96 © 2009 Microchip Technology Inc. ...
Page 97
... TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
Page 98
... PIC18F2682/2685/4682/4685 FIGURE 6-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”. ...
Page 99
... RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 R/W-0 R/W-x R/W-0 (1) FREE ...
Page 100
... PIC18F2682/2685/4682/4685 6.2.2 TABLAT – TABLE LATCH REGISTER The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TBLPTR – TABLE POINTER REGISTER The Table Pointer (TBLPTR) register addresses a byte within the program memory ...
Page 101
... MOVF TABLAT, W MOVF WORD_ODD © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT ...
Page 102
... PIC18F2682/2685/4682/4685 6.4 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be Bulk Erased. Word Erase in the Flash array is not supported. When initiating an erase sequence from the micro- controller itself, a block of 64 bytes of program memory is erased ...
Page 103
... CFGS bit to access program memory; • set WREN to enable byte writes. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer ...
Page 104
... PIC18F2682/2685/4682/4685 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D'64 MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_BLOCK TBLRD*+ MOVF TABLAT, W MOVWF POSTINC0 DECFSZ COUNTER BRA READ_BLOCK ...
Page 105
... OSCFIE CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: These bits are available in PIC18F4682/4685 devices and reserved in PIC18F2682/2685 devices. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 ; point to Flash program memory ; access Flash program memory ...
Page 106
... PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 106 © 2009 Microchip Technology Inc. ...
Page 107
... EEPROM. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 The EECON1 register (Register 7-1) is the control register for data and program memory access. Control bit EEPGD determines if the access will be to program or data EEPROM memory ...
Page 108
... PIC18F2682/2685/4682/4685 REGISTER 7-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 EEPGD CFGS — bit 7 Legend Settable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory ...
Page 109
... BSF INTCON, GIE BCF EECON1, WREN © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM ...
Page 110
... PIC18F2682/2685/4682/4685 7.6 Operation During Code-Protect Data EEPROM memory has its own code-protect bits in Configuration Words. External read operations are disabled if code protection is enabled. The microcontroller itself can both read and write to the internal Data EEPROM, regardless of the state of the code-protect Configuration bit. Refer to Section 24.0 “ ...
Page 111
... OSCFIF CMIF (1) PIE2 OSCFIE CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: These bits are available in PIC18F4682/4685 devices and reserved in PIC18F2682/2685 devices. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Bit 5 Bit 4 Bit 3 Bit 2 INT0IE ...
Page 112
... PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 112 © 2009 Microchip Technology Inc. ...
Page 113
... Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 EXAMPLE 8-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 8-2: MOVF ARG1, W MULWF ARG2 BTFSC ARG2, SB ...
Page 114
... PIC18F2682/2685/4682/4685 Example 8-3 shows the sequence unsigned multiplication. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 8- UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L • ARG2H:ARG2L RES3:RES0 = 16 (ARG1H • ARG2H • (ARG1H • ARG2L • (ARG1L • ARG2H • 2 (ARG1L • ...
Page 115
... INTERRUPTS The PIC18F2682/2685/4682/4685 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 000008h and the low priority interrupt vector is at 000018h. High priority interrupt events will interrupt any low priority interrupts that may be in progress ...
Page 116
... PIC18F2682/2685/4682/4685 FIGURE 9-1: INTERRUPT LOGIC Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit TMR1IF TMR1IE TMR1IP XXXXIF XXXXIE XXXXIP Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit ...
Page 117
... Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit ...
Page 118
... PIC18F2682/2685/4682/4685 REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values ...
Page 119
... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 R/W-0 R/W-0 U-0 ...
Page 120
... TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software TMR1 register did not overflow Note 1: This bit is reserved on PIC18F2682/2685 devices; always maintain this bit clear. DS39761C-page 120 Note 1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit, GIE (INTCON< ...
Page 121
... No TMR1 register capture occurred Compare mode TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM mode: Unused in this mode. Note 1: These bits are available in PIC18F4682/4685 and reserved in PIC18F2682/2685 devices. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 R/W-0 R/W-0 R/W-0 EEIF ...
Page 122
... PIC18F2682/2685/4682/4685 REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 Mode 0 IRXIF WAKIF R/W-0 R/W-0 Mode 1,2 IRXIF WAKIF bit 7 Legend Readable bit -n = Value at POR bit 7 IRXIF: CAN Invalid Received Message Interrupt Flag bit invalid message has occurred on the CAN bus ...
Page 123
... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: This bit is reserved on PIC18F2682/2685 devices; always maintain this bit clear. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 R/W-0 R/W-0 R/W-0 ...
Page 124
... PIC18F2682/2685/4682/4685 REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 U-0 (1) OSCFIE CMIE — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit ...
Page 125
... When CAN is in Mode 2: FIFOWMIE: FIFO Watermark Interrupt Enable bit 1 = Enable FIFO watermark interrupt 0 = Disable FIFO watermark interrupt Note 1: In CAN Mode 1 and 2, these bits are forced to ‘0’. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 R/W-0 R/W-0 R/W-0 (1) ERRIE TXB2IE TXB1IE ...
Page 126
... TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: This bit is reserved on PIC18F2682/2685 devices; always maintain this bit clear. DS39761C-page 126 R/W-1 R/W-1 R/W-1 TXIP SSPIP CCP1IP U = Unimplemented bit, read as ‘ ...
Page 127
... Low priority bit 0 ECCP1IP: ECCP1 Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: These bits are available on PIC18F4682/4685 devices only. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 R/W-1 R/W-1 R/W-1 EEIP BCLIP HLVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 128
... PIC18F2682/2685/4682/4685 REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 Mode 0 IRXIP WAKIP R/W-1 R/W-1 Mode 1,2 IRXIP WAKIP bit 7 Legend Readable bit -n = Value at POR bit 7 IRXIP: CAN Invalid Received Message Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 WAKIP: CAN bus Activity Wake-up Interrupt Priority bit ...
Page 129
... For details of bit operation, see Register 4-1. Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise ‘0’. 2: The actual Reset value of POR is determined by the type of device Reset. See Register 4-1 for additional information. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 R/W-1 R-1 R Unimplemented bit, read as ‘ ...
Page 130
... PIC18F2682/2685/4682/4685 9.6 INTx Pin Interrupts External interrupts on the RB0/INT0, RB1/INT1 and RB2/INT2 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxIF, is set ...
Page 131
... EN RD PORT Note 1: I/O pins have diode protection to V © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 10.1 PORTA, TRISA and LATA Registers PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i ...
Page 132
... OSC1/CLKI/RA7 OSC1 IN CLKI IN RA7 OUT IN Legend: OUT = Output Input; ANA = Analog Signal; DIG = Digital Output Schmitt Buffer Input; TTL = TTL Buffer Input Note 1: This bit is unimplemented on PIC18F2682/2685 devices. DS39761C-page 132 TRIS Buffer DIG LATA<0> data output. 0 TTL PORTA<0> data input. 1 ANA A/D input channel 0 ...
Page 133
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. 2: These registers are unimplemented on PIC18F2682/2685 devices. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Bit 5 Bit 4 ...
Page 134
... PIC18F2682/2685/4682/4685 10.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i ...
Page 135
... IN KBI3 IN PGD OUT IN Legend: OUT = Output Input; ANA = Analog Signal; DIG = Digital Output Schmitt Buffer Input; TTL – TTL Buffer Input Note 1: This bit is unimplemented on PIC18F2682/2685 devices. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TRIS Buffer DIG LATB<0> data output. 0 TTL PORTB<0> data input. Weak pull-up available only in this mode. ...
Page 136
... PIC18F2682/2685/4682/4685 TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 Bit 6 PORTB RB7 RB6 LATB LATB Data Output Register TRISB PORTB Data Direction Register INTCON GIE/GIEH PEIE/GIEL TMR0IE INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTCON3 INT2IP INT1IP ADCON1 — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB. ...
Page 137
... TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Note Power-on Reset, these pins are configured as digital inputs. The contents of the TRISC register are affected by peripheral overrides ...
Page 138
... PIC18F2682/2685/4682/4685 TABLE 10-5: PORTC I/O SUMMARY Pin Name Function I/O TRIS RC0/T1OSO/ RC0 OUT 0 T13CKI IN 1 T1OSO OUT x T13CKI IN 1 RC1/T1OSI RC1 OUT T1OSI IN x RC2/CCP1 RC2 OUT CCP1 OUT RC3/SCK/SCL RC3 OUT SCK OUT SCL OUT RC4/SDI/SDA RC4 OUT 0 IN ...
Page 139
... TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 PORTC RC7 RC6 LATC LATC Data Output Register TRISC PORTC Data Direction Register © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 Reset Bit 1 Bit 0 Values ...
Page 140
... PIC18F2682/2685/4682/4685 10.4 PORTD, TRISD and LATD Registers Note: PORTD is only available on PIC18F4682/ 4685 devices. PORTD is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode) ...
Page 141
... DIG 0 Legend: OUT = Output Input; ANA = Analog Signal; DIG = Digital Output Schmitt Buffer Input; TTL = TTL Buffer Input © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Description LATD<0> data output. ST PORTD<0> data input. Parallel Slave Port (PSP) data output (overrides the TRIS<0> control when enabled). ...
Page 142
... PIC18F2682/2685/4682/4685 TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Name Bit 7 Bit 6 (1) PORTD RD7 RD6 (1) LATD LATD Data Output Register (1) TRISD PORTD Data Direction Register (1) TRISE IBF OBF (1) ECCP1CON EPWM1M1 EPWM1M0 EDC1B1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. ...
Page 143
... MOVWF CMCON MOVWF TRISC 10.5.1 PORTE IN 28-PIN DEVICES For PIC18F2682/2685 devices, PORTE is only available when Master Clear functionality is disabled (MCLRE = 0). In these cases, PORTE is a single bit, input only port comprised of RE3 only. The pin operates as previously described. /RE3 input PP INITIALIZING PORTE ...
Page 144
... PIC18F2682/2685/4682/4685 REGISTER 10-1: TRISE REGISTER (PIC18F4682/4685 DEVICES ONLY) R-0 R-0 R/W-0 IBF OBF IBOV bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IBF: Input Buffer Full Status bit word has been received and waiting to be read by the CPU ...
Page 145
... Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0). 2: RE3 is the only PORTE bit implemented on both PIC18F2682/2685 and PIC18F4682/4685 devices. All other bits are implemented only when PORTE is implemented (i.e., PIC18F4682/4685 devices). 3: These registers are unimplemented on PIC18F2682/2685 devices. ...
Page 146
... PIC18F2682/2685/4682/4685 10.6 Parallel Slave Port Note: The Parallel Slave Port is only available on PIC18F4682/4685 devices. In addition to its function as a general I/O port, PORTD can also operate as an 8-bit wide Parallel Slave Port (PSP) or microprocessor port. PSP operation is controlled by the 4 upper bits of the TRISE register (Register 10-1) ...
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... C2OUT C1OUT Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. Note 1: These registers are available on PIC18F4682/4685 devices only. 2: These bits are unimplemented on PIC18F2682/2685 devices and read as ‘0’. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 ...
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... PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 148 © 2009 Microchip Technology Inc. ...
Page 149
... Prescale value 000 = 1:2 Prescale value © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 11-1 ...
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... PIC18F2682/2685/4682/4685 11.1 Timer0 Operation Timer0 can operate as either a timer or a counter; the mode is selected by clearing (T0CON<5>). In Timer mode, the module increments on every clock by default unless a different prescaler value is selected (see Section 11.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register ...
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... Legend unknown unchanged, — = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0. Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 11.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “ ...
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... PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 152 © 2009 Microchip Technology Inc. ...
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... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 A simplified block diagram of the Timer1 module is shown in Figure 12-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 12-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
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... PIC18F2682/2685/4682/4685 12.1 Timer1 Operation Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS is cleared (= 0), Timer3 increments on every internal instruction FIGURE 12-1: TIMER1 BLOCK DIAGRAM ...
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... XTAL 32.768 kHz T1OSO Note: See the Notes with Table 12-1 for additional information about capacitor selection. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 12-1: CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR Osc Type Freq LP 32.768 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
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... PIC18F2682/2685/4682/4685 12.3.3 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 12-3, should be located as close as possible to the microcontroller. ...
Page 157
... T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend unknown unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Note 1: These bits are unimplemented on PIC18F2682/2685 devices; always maintain these bits clear. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 ; Preload TMR1 register pair ...
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... PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 158 © 2009 Microchip Technology Inc. ...
Page 159
... Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 13.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 2-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide- by-16 prescale options ...
Page 160
... PR2 Timer2 Period Register Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module. Note 1: These bits are unimplemented on PIC18F2682/2685 devices; always maintain these bits clear. DS39761C-page 160 13.3 TMR2 Output The unscaled output of TMR2 is available primarily to the CCP1 modules, where it is used as a time base for operations in PWM mode ...
Page 161
... Stops Timer3 Note 1: Thess bits and the ECCP1 module are available on PIC18F4682/4685 devices only. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 A simplified block diagram of the Timer3 module is shown in Figure 14-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 14-2. The Timer3 module is controlled through the T3CON register (Register 14-1) ...
Page 162
... PIC18F2682/2685/4682/4685 14.1 Timer3 Operation Timer3 can operate in one of three modes: • Timer • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS is cleared (= 0), Timer3 increments on every internal instruction FIGURE 14-1: TIMER3 BLOCK DIAGRAM ...
Page 163
... RD16 T3ECCP1 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. Note 1: These bits are unimplemented on PIC18F2682/2685 devices; always maintain these bits clear. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 14.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h ...
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... PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 164 © 2009 Microchip Technology Inc. ...
Page 165
... CAPTURE/COMPARE/PWM (CCP1) MODULES PIC18F2682/2685 devices have one CCP1 module. PIC18F4682/4685 devices have two CCP1 (Capture/ Compare/PWM) modules. CCP1, discussed in this chapter, implements standard Capture, Compare and Pulse-Width Modulation (PWM) modes. ECCP1 implements an Enhanced PWM mode. The ECCP1 implementation is discussed in Section 16.0 “ ...
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... PIC18F2682/2685/4682/4685 15.1 CCP1 Module Configuration Each Capture/Compare/PWM module is associated with a control register (CCP1CON or ECCP1CON) and a data register (CCPR1 or ECCPR1). The data register, in turn, is comprised of two 8-bit registers: CCPR1L or ECCPR1L (low byte) and CCPR1H or ECCPR1H (high byte). All registers are both readable and writable. ...
Page 167
... CCP1IE or ECCP1IE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCP1IF or ECCP1IF, should also be cleared following any such change in operating mode. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 15.2.4 CCP1 PRESCALER There are four prescaler settings in Capture mode; they (or are specified as part of the operating mode selected by the mode select bits (CCP1M3:CCP1M0) ...
Page 168
... PIC18F2682/2685/4682/4685 FIGURE 15-1: CAPTURE MODE OPERATION BLOCK DIAGRAM CCP1 pin Prescaler ÷ CCP1CON<3:0> Q1:Q4 ECCP1CON<3:0> ECCP1 pin Prescaler ÷ DS39761C-page 168 Set CCP1IF T3ECCP1 and Edge Detect T3ECCP1 4 Set ECCP1IF 4 4 T3CCP1 T3ECCP1 and Edge Detect T3ECCP1 T3CCP1 TMR3H TMR3L TMR3 ...
Page 169
... TMR3L T3CCP1 Comparator ECCPR1H ECCPR1L © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 15.3.2 TIMER1/TIMER3 MODE SELECTION Timer1 and/or Timer3 must be running in Timer mode or Synchronized Counter mode if the CCP1 module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. ...
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... PIC18F2682/2685/4682/4685 TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL (2) RCON IPEN SBOREN (1) IPR1 PSPIP ADIP (1) PIR1 PSPIF ADIF (1) PIE1 PSPIE ADIE (1) IPR2 OSCFIP CMIP (1) OSCFIF PIR2 CMIF (1) OSCFIE PIE2 CMIE TRISB PORTB Data Direction Register ...
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... A PWM output (Figure 15-4) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/ period). © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 FIGURE 15-4: Duty Cycle TMR2 = PR2 15.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 (PR4) register ...
Page 172
... PIC18F2682/2685/4682/4685 The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. ...
Page 173
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2. Note 1: These bits or registers are available on PIC18F4682/4685 devices only. 2: The SBOREN bit is only available when CONFIG2L<1:0> = © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INT0IE ...
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... PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 174 © 2009 Microchip Technology Inc. ...
Page 175
... ECCP1 module are the same as described for the standard CCP1 module. The control register for the Enhanced CCP1 module is shown in Register 16-1. It differs from the CCP1CON register in the PIC18F2682/2685 devices in that the two Most Significant bits are implemented to control PWM functionality. R/W-0 ...
Page 176
... PIC18F2682/2685/4682/4685 In addition to the expanded range of modes available through the ECCP1CON register, the ECCP1 module has two additional registers associated with Enhanced PWM operation and auto-shutdown features. They are: • ECCP1DEL (Dead-Band Delay) • ECCP1AS (Auto-Shutdown Configuration) 16.1 ECCP1 Outputs and Configuration ...
Page 177
... D.C. PR2 Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 16.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following equation ...
Page 178
... PIC18F2682/2685/4682/4685 16.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the ECCPR1L register and to the ECCP1CON<5:4> bits 10-bit resolution is available. The ECCPR1L contains the eight MSbs and the ECCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by ECCPR1L:ECCP1CON<5:4>. The PWM duty cycle is calculated by the following equation ...
Page 179
... Prescale Value) OSC • Duty Cycle = T * (ECCPR1L<7:0>:ECCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (ECCP1DEL<6:0>) OSC Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 16.4.6 “Programmable Dead-Band Delay”). © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 0 Duty Cycle Period (1) Delay Delay 0 Duty ...
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... PIC18F2682/2685/4682/4685 16.4.4 HALF-BRIDGE MODE In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the P1A pin, while the complemen- tary PWM output signal is output on the P1B pin (Figure 16-4). This mode can be used for half-bridge ...
Page 181
... Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 P1A, P1B, P1C and P1D outputs are multiplexed with the PORTD<4>, PORTD<7> data latches. The TRISD<4>, TRISD<5>, TRISD<6> and TRISD<7> bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs ...
Page 182
... PIC18F2682/2685/4682/4685 FIGURE 16-7: EXAMPLE OF FULL-BRIDGE APPLICATION PIC18F268X/468X P1A P1B P1C P1D 16.4.5.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the EPWM1M1 bit in the ECCP1CON register allows the user to control the forward/reverse direction. When the firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle ...
Page 183
... All signals are shown as active-high the turn-on delay of power switch QC and its driver the turn-off delay of power switch QD and its driver. OFF © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 (1) Period depending on the Timer2 prescaler value. The modulated P1B and OSC OSC Forward Period t1 DC ...
Page 184
... T ). These bits are not available on CY OSC PIC18F2682/2685 devices, as the standard CCP1 module does not support half-bridge operation. 16.4.7 ENHANCED PWM AUTO-SHUTDOWN When the ECCP1 is programmed for any of the Enhanced PWM modes, the active output pins may be ...
Page 185
... PSSBD1:PSSBD0: Pins B and D Shutdown State Control bits 1x = Pins B and D tri-state 01 = Drive Pins B and D to ‘1’ Drive Pins B and D to ‘0’ Note 1: This register is available on PIC18F4682/4685 devices only. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 (1) R/W-0 R/W-0 R/W-0 ECCPAS0 PSSAC1 PSSAC0 U = Unimplemented bit, read as ‘ ...
Page 186
... PIC18F2682/2685/4682/4685 16.4.7.1 Auto-Shutdown and Auto-Restart The auto-shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. This is enabled by setting the PRSEN bit of the ECCP1DEL register (ECCP1DEL<7>). In Shutdown mode with PRSEN = 1 (Figure 16-10), the ECCPASE bit will remain set for as long as the cause of the shutdown continues ...
Page 187
... P1D pin outputs by clearing the respective TRIS bits. • Clear the ECCPASE bit (ECCP1AS<7>). © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 16.4.10 EFFECTS OF A RESET Both Power-on Reset and subsequent Resets will force all ports to Input mode and the ECCP1 registers to their Reset states ...
Page 188
... Shaded cells are not used during ECCP1 operation. Note 1: These registers are available on PIC18F4682/4685 devices only. 2: These bits are available on PIC18F4682/4685 and reserved on PIC18F2682/2685 devices. 3: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise disabled and reads as ‘0’. DS39761C-page 188 ...
Page 189
... MSSP 2 module is operating in SPI mode. Additional details are provided under the individual sections. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 17.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of ...
Page 190
... PIC18F2682/2685/4682/4685 17.3.1 REGISTERS The MSSP module has four registers for SPI mode operation. These are: • MSSP Control Register 1 (SSPCON1) • MSSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer Register (SSPBUF) • MSSP Shift Register (SSPSR) – Not directly accessible SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation ...
Page 191
... In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 R/W-0 R/W-0 R/W-0 (2) (3) CKP ...
Page 192
... PIC18F2682/2685/4682/4685 17.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>). These control bits allow the following to be specified: • Master mode (SCK is the clock output) • Slave mode (SCK is the clock input) • ...
Page 193
... Shift Register (SSPSR) LSb MSb PROCESSOR 1 © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 17.3.4 TYPICAL CONNECTION Figure 17-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock ...
Page 194
... PIC18F2682/2685/4682/4685 17.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 17- broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input) ...
Page 195
... Flag SSPSR to SSPBUF © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 must be high. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte, and becomes a floating output ...
Page 196
... PIC18F2682/2685/4682/4685 FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF FIGURE 17-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) ...
Page 197
... SSPSTAT SMP CKE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. Note 1: These bits are unimplemented in PIC18F2682/2685 devices; always maintain these bits clear. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 17.3.9 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer ...
Page 198
... PIC18F2682/2685/4682/4685 2 17 Mode 2 The MSSP module mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing ...
Page 199
... This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 2 C™ MODE) R-0 R-0 ...
Page 200
... PIC18F2682/2685/4682/4685 REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER 1 (I R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 WCOL: Write Collision Detect bit In Master Transmit mode write to the SSPBUF register was attempted while the I ...