PIC18F6627-E/PT Microchip Technology, PIC18F6627-E/PT Datasheet - Page 19

• Manufacturer Part Number: PIC18F6627-E/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6627-E/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 96KB (48K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.2.2
The previous programming example assumed that the
device has been Bulk Erased prior to programming (see
Section 3.1.1 “High-Voltage ICSP Bulk Erase”). It
may be the case, however, that the user wishes to
modify only a section of an already programmed device.
TABLE 3-6:
© 2009 Microchip Technology Inc.
Step 1: Direct access to code memory.
Step 2: Read and modify code memory (see Section 4.1 “Read Code Memory, ID Locations and Configuration Bits”).
Step 3: Set the Table Pointer for the block to be erased.
Step 4: Enable memory writes and set up an erase.
Step 5: Initiate erase.
Step 6: Direct access to configuration memory.
Step 7: Direct access to code memory and enable writes.
Step 8: Load write buffer. The correct bytes will be selected based on the Table Pointer.
To continue modifying data, repeat Steps 2 through 8, where the Address Pointer is incremented by the 64 bytes at each iteration of
the loop.
Step 9: Disable writes.
Command
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1101
1111
0000
0000
4-Bit
.
.
.
MODIFYING CODE MEMORY
8E A6
9C A6
0E <Addr[21:16]>
6E F8
0E <Addr[8:15]>
6E F7
0E <Addr[7:0]>
6E F6
84 A6
88 A6
82 A6
00 00
8E A6
8C A6
84 A6
8E A6
9C A6
0E <Addr[21:16]>
6E F8
0E <Addr[8:15]>
6E F7
0E <Addr[7:0]>
6E F6
<MSB><LSB>
<MSB><LSB>
00 00
94 A6
MODIFYING CODE MEMORY
Data Payload
.
.
.
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BSF
NOP - hold PGC high for time P9 and low for time P10.
BSF
BSF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
Write 2 bytes and post-increment address by 2.
Repeat 28 times
Write 2 bytes and start programming.
NOP - hold PGC high for time P9 and low for time P10.
BCF
EECON1, EEPGD
EECON1, CFGS
<Addr[21:16]>
TBLPTRU
<Addr[8:15]>
TBLPTRH
<Addr[7:0]>
TBLPTRL
EECON1, WREN
EECON1, FREE
EECON1, WR
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
EECON1, EEPGD
EECON1, CFGS
<Addr[21:16]>
TBLPTRU
<Addr[8:15]>
TBLPTRH
<Addr[7:0]>
TBLPTRL
EECON1, WREN
The appropriate number of bytes required for the erase
buffer must be read out of code memory (as described
in Section 4.2 “Verify Code Memory and ID Loca-
tions”) and buffered. Modifications can be made on
this buffer. Then, the block of code memory that was
read out must be erased and rewritten with the
modified data (see Section 3.2.1 “Programming”).
The WREN bit must be set if the WR bit in EECON1 is
used to initiate a write sequence.
PIC18F872X FAMILY
Core Instruction
DS39643C-page 19