PIC18F6722-E/PT Microchip Technology, PIC18F6722-E/PT Datasheet - Page 27

• Manufacturer Part Number: PIC18F6722-E/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6722-E/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11
• Lead Free Status / Rohs Status: Details

4.3
A configuration address may be read and output on
PGD via the 4-bit command, ‘1001’. Configuration data
is read and written in a byte-wise fashion, so it is not
necessary to merge two bytes into a word prior to a
compare. The result may then be immediately
compared to the appropriate configuration data in the
programmer’s memory for verification. Refer to
Section 4.1 “Read Code Memory, ID Locations and
Configuration Bits” for implementation details of
reading configuration data.
4.4
Data EEPROM is accessed one byte at a time via an
Address Pointer (register pair, EEADRH:EEADR) and
a data latch (EEDATA). Data EEPROM is read by
loading EEADRH:EEADR with the desired memory
location and initiating a memory read by appropriately
configuring the EECON1 register (Register 3-1). The
data will be loaded into EEDATA, where it may be
serially output on PGD via the 4-bit command, ‘0010’
(Shift Out Data Holding register). A delay of P6 must be
introduced after the falling edge of the 8th PGC of the
operand to allow PGD to transition from an input to an
output. During this time, PGC must be held low (see
Figure 4-4).
The command sequence to read a single byte of data
is shown in Table 4-2.
TABLE 4-2:
© 2009 Microchip Technology Inc.
Step 1: Direct access to data EEPROM.
Step 2: Set the data EEPROM Address Pointer.
Step 3: Initiate a memory read.
Step 4: Load data into the Serial Data Holding register.
Note 1:
Command
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0010
4-Bit
Verify Configuration Bits
Read Data EEPROM Memory
The <LSB> is undefined. The <MSB> is the data.
9E A6
9C A6
0E <Addr>
6E A9
OE <AddrH>
6E AA
80 A6
50 A8
6E F5
00 00
<MSB><LSB>
READ DATA EEPROM MEMORY
Data Payload
BSF
BCF
BCF
MOVLW <Addr>
MOVWF EEADR
MOVLW <AddrH>
MOVWF EEADRH
MOVF
MOVWF TABLAT
NOP
Shift Out Data
EECON1, EEPGD
EECON1, CFGS
EECON1, RD
EEDATA, W, 0
(1)
FIGURE 4-3:
PIC18F872X FAMILY
Core Instruction
No
Move to TABLAT
READ DATA EEPROM
FLOW
Shift Out Data
Address
Done?
Read
Done
Start
Byte
Set
Yes
DS39643C-page 27