PIC18F8620-E/PT Microchip Technology, PIC18F8620-E/PT Datasheet
PIC18F8620-E/PT
Specifications of PIC18F8620-E/PT
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PIC18F8620-E/PT Summary of contents
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... This document includes the specifications for the following devices: • PIC18F6520 • PIC18F6620 • PIC18F6720 • PIC18F8520 • PIC18F8620 • PIC18F8720 2.0 PROGRAMMING OVERVIEW OF THE PIC18FXX20 PIC18FXX20 devices can be programmed using either the high voltage In-Circuit Serial Programming (ICSP TM ) method, or the low voltage ICSP method. ...
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... PIC18F6520 44 PIC18F6620 43 PIC18F6720 64L TQFP RH2 1 RH3 2 RE1 3 RE0 4 RG0 5 RG1 6 RG2 PIC18F8520 7 RG3 8 PIC18F8620 9 PP RG4 10 PIC18F8720 80L TQFP RF7 13 RF6 14 RF5 15 RF4 16 RF3 17 RF2 18 RH7 19 RH6 RB0 RB1 RB2 RB3 RB4 RB5 RB6 V SS OSC2/RA6 OSC1 V DD RB7 ...
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... Read as ‘0’ 1FFFFFh Configuration and ID Space 3FFFFFh Note: Sizes of memory areas not to scale. 2010 Microchip Technology Inc. TABLE 2-2: Device PIC18F6520 PIC18F8520 PIC18F6620 PIC18F8620 PIC18F6720 PIC18F8720 MEMORY SIZE / DEVICE 32 Kbytes Address 64 Kbytes (PIC18FX520) Range (PIC18FX620) 000000h Boot Block Boot Block 0007FFh ...
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... ID Location 8 CONFIG1L CONFIG1H CONFIG2L CONFIG2H CONFIG3L CONFIG3H CONFIG4L CONFIG4H CONFIG5L CONFIG5H CONFIG6L CONFIG6H CONFIG7L CONFIG7H Device ID1 Device ID2 2010 Microchip Technology Inc. TBLPTRL Addr[7:0] 200000h 200001h 200002h 200003h 200004h 200005h 200006h 200007h 300000h 300001h 300002h 300003h 300004h 300005h 300006h ...
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... ENTERING HIGH VOLTAGE PROGRAM/ VERIFY MODE P13 P12 P1 D110 MCLR SDATA SCLK SDATA = Input 2010 Microchip Technology Inc. PIC18FXX20 FIGURE 2-4: HIGH LEVEL PROGRAMMING FLOW Start Perform Bulk Erase Program Memory Program IDs Program Data Verify Program Verify IDs Verify Data ...
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... Data Payload SDATA = Input COMMANDS FOR PROGRAMMING 4-Bit Description Command 0000 0010 1000 1001 1010 1011 1100 1101 1110 1111 SAMPLE COMMAND SEQUENCE Data Core Instruction Payload 3C 40 Table Write, post-increment P5A Fetch Next 4-bit Command 2010 Microchip Technology Inc. ...
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... SDATA 4-bit Command 16-bit Data Payload 2010 Microchip Technology Inc. Note: A bulk erase is the only way to reprogram code protect bits from an on-state to an off-state. Non-code protect bits are not returned to default settings by a bulk erase. These bits should be programmed to ones, as out- lined in Section 3.6, " ...
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... Programming” command, and parameters P9 and P10 is shown in Figure 3-7. Note: The TBLPTR register must contain the same offset value when initiating the pro- gramming sequence as it did when the write buffers were loaded. 2010 Microchip Technology Inc. ...
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... Step 5: Repeat step 4, with Address Pointer incremented by 64 until all panels are erased. FIGURE 3-4: MULTI-PANEL SINGLE ROW ERASE CODE MEMORY FLOW Addr = Addr + 64 2010 Microchip Technology Inc. Core Instruction BSF EECON1, EEPGD BSF EECON1, CFGS BSF ...
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... Programming” command, and parameters P9 and P10, is shown in Figure 3-7. Note: The TBLPTR register must contain the same offset value when initiating the pro- gramming sequence as it did when the write buffers were loaded. 2010 Microchip Technology Inc. ...
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... Offset = TBLPTR<12:3> Panel 1 TBLPTR<21:13> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> Offset = TBLPTR<12:3> Note: TBLPTR = TBLPTRU:TBLPTRH:TBLPTRL. 2010 Microchip Technology Inc. PIC18FXX20 Erase Region (64 bytes) Offset = TBLPTR<12:6> Erase Region (64 bytes) Offset = TBLPTR<12:6> Erase Region (64 bytes) Offset = TBLPTR<12:6> Erase Region (64 bytes) Offset = TBLPTR< ...
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... MOVLW <Addr[15:8]> MOVWF TBLPTRH MOVLW <Addr[7:0]> MOVWF TBLPTRL Write 2 bytes and post-increment address by 2 Write 2 bytes and post-increment address by 2 Write 2 bytes and post-increment address by 2 Write 2 bytes and start programming NOP - hold SCLK high for time P9 2010 Microchip Technology Inc. ...
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... TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111 SCLK P5 SDATA 4-bit Command 2010 Microchip Technology Inc. Start LoopCount = 0 Configure Device for Multi-Panel Writes Panel Base Address = (N – 2000h Addr = Panel Base Address + (8 x LoopCount) Load 8 Bytes to Panel N Write Buffer at <Addr> All No ...
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... The erase will begin on the falling edge of the 4th SCLK, after the WR bit is set. After the erase sequence terminates, SCLK must still be held low for the time specified by parameter #P10 to allow high voltage discharge of the memory array. 2010 Microchip Technology Inc. ...
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... To continue writing data, repeat step 8, where the Address Pointer is incremented each iteration of the loop. 2010 Microchip Technology Inc. Core Instruction BSF EECON1, EEPGD BSF EECON1, CFGS MOVLW 3Ch MOVWF TBLPTRU MOVLW 00h ...
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... Start Set Address Set Data Enable Write Unlock Sequence 55h - EECON2 AAh - EECON2 Start Write Sequence No WR bit Clear ? Yes No Done ? Yes Done P10 16-bit Data Payload P5A Shift Out Data (see Figure 4-6) SDATA = Output 2010 Microchip Technology Inc. ...
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... Step 8: Disable writes. 0000 94 A6 Repeat steps 2 through 8 to write more data. Note 1: See Figure 4-4 for details on Shift Out Data timing. 2010 Microchip Technology Inc. Core Instruction BCF EECON1, EEPGD BCF EECON1, CFGS MOVLW <Addr> MOVWF EEADR MOVLW < ...
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... MOVLW 00h MOVWF TBLPTRH MOVLW 00h MOVWF TBLPTRL Write 2 bytes and post-increment address by 2 Write 2 bytes and post-increment address by 2 Write 2 bytes and post-increment address by 2 Write 2 bytes and start programming NOP - hold SCLK high for time P9 2010 Microchip Technology Inc. ...
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... Address Program LSB Delay P9 Time for Write Done 2010 Microchip Technology Inc. 3.6 Configuration Bits Programming Unlike code memory, the configuration bits are programmed a byte at a time. The “Table Write, Begin Programming” 4-bit command (1111) is used, but only 8 bits of the following 16-bit payload will be written. The LSB of the payload will be written to even addresses, and the MSB will be written to odd addresses ...
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... ID and Configuration registers. Core Instruction MOVLW Addr[21:16] MOVWF TBLPTRU MOVLW <Addr[15:8]> MOVWF TBLPTRH MOVLW <Addr[7:0]> MOVWF TBLPTRL TBLRD *+ P14 3 LSb 1 2 Shift Data Out SDATA = Output P5A 4 MSb Fetch Next 4-bit Command SDATA = Input 2010 Microchip Technology Inc. ...
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... All No Code Memory Verified? Yes 2010 Microchip Technology Inc. The Table Pointer must be manually set to 200000h (base address of the ID locations), once the code memory has been verified. The post-increment feature of the Table Read 4-bit command may not be used to increment the Table Pointer beyond the code memory space ...
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... During this time, SCLK must be held low (see Figure 4-4). The command sequence to read a single byte of data is shown in Figure 4-2. DS39583C-page 22 FIGURE 4-3: READ DATA EEPROM FLOW Start Set Address Read Byte Move to TABLAT Shift Out Data No Done ? Yes Done 2010 Microchip Technology Inc. ...
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... SHIFT OUT DATA HOLDING REGISTER TIMING (0010 SCLK P5 SDATA SDATA = Input 2010 Microchip Technology Inc. Core Instruction BCF EECON1, EEPGD BCF EECON1, CFGS MOVLW <Addr> MOVWF EEADR MOVLW <AddrH> MOVWF EEADRH BSF EECON1, RD MOVF EEDATA MOVWF TABLAT (1) Shift Out Data 9 10 ...
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... Given that “Blank Checking” is merely code and data EEPROM verification with FFh expect data, refer to Section 4.4 and Section 4.2 for implementation details. FIGURE 4-5: Start Blank Check Device Device Blank? Abort for blank BLANK CHECK FLOW Is Yes Continue No 2010 Microchip Technology Inc. ...
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... TABLE 5-1: DEVICE ID VALUES Device PIC18F6520 PIC18F6620 PIC18F6720 PIC18F8520 PIC18F8620 PIC18F8720 Note: The ‘x’s in DEVID1 contain the device revision code. 2010 Microchip Technology Inc. PIC18FXX20 5.3 Low Voltage Programming (LVP) Bit The LVP bit in Configuration register, CONFIG4L, enables low voltage ICSP programming ...
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... STVREN 1000 0101 CP1 CP0 1111 1111 — — 1100 0000 WRT1 WRT0 1111 1111 — — 1110 0000 EBTR1 EBTR0 1111 1111 — — 0100 0000 REV1 REV0 Table 5-1 DEV4 DEV3 Table 5-1 2010 Microchip Technology Inc. ...
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... CONFIG3L Note 1: Unimplemented in PIC18F6X20 (64-pin) devices; maintain this bit set. 2: Unimplemented in PIC18FX620 devices; maintain this bit set. 3: PIC18F8520/8620 devices only. 2010 Microchip Technology Inc. Description Low Power System Clock Option (Timer1) Enable bit 1 = Disabled 0 = Timer1 oscillator system clock option enabled ...
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... Code Protection bits (Block Code memory not code protected 0 = Code memory code protected Code Protection bits (Block Code memory not code protected 0 = Code memory code protected Code Protection bits (Block Code memory not code protected 0 = Code memory code protected 2010 Microchip Technology Inc. ...
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... WRTC CONFIG6H Note 1: Unimplemented in PIC18F6X20 (64-pin) devices; maintain this bit set. 2: Unimplemented in PIC18FX620 devices; maintain this bit set. 3: PIC18F8520/8620 devices only. 2010 Microchip Technology Inc. Description Code Protection bits (Data EEPROM Data EEPROM not code protected 0 = Data EEPROM code protected ...
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... These bits are used with the DEV2:DEV0 bits in the DEVID1 register to identify part number. Device ID bits These bits are used with the DEV10:DEV3 bits in the DEVID2 register to identify part number. These bits are used to indicate the revision of the device. 2010 Microchip Technology Inc. ...
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... An option to not include the configuration word information may be provided. When embedding configuration word information in the HEX file, it should start at address 300000h. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. 2010 Microchip Technology Inc. 5.5 ...
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... Description CFGW = Configuration Word SUM[a:b] = Sum of locations inclusive SUM_ID = Byte-wise sum of lower four bits of all customer ID locations + = Addition & = Bit-wise AND DS39583C-page 32 Checksum 2010 Microchip Technology Inc. 0xAA at 0 Blank and Max Value Address 05A8 04FE 077F 734 857C 8531 ...
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... Legend: Item Description CFGW = Configuration Word SUM[a:b] = Sum of locations inclusive SUM_ID = Byte-wise sum of lower four bits of all customer ID locations + = Addition & = Bit-wise AND 2010 Microchip Technology Inc. PIC18FXX20 Checksum 0xAA at 0 Blank and Max Value Address 02D8 022E 04AF ...
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... Description CFGW = Configuration Word SUM[a:b] = Sum of locations inclusive SUM_ID = Byte-wise sum of lower four bits of all customer ID locations + = Addition & = Bit-wise AND DS39583C-page 34 Checksum 2010 Microchip Technology Inc. 0xAA at 0 Blank and Max Value Address 05A8 04FE 077F 0734 857C 8531 ...
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... Legend: Item Description CFGW = Configuration Word SUM[a:b] = Sum of locations inclusive SUM_ID = Byte-wise sum of lower four bits of all customer ID locations + = Addition & = Bit-wise AND 2010 Microchip Technology Inc. PIC18FXX20 Checksum 0xAA at 0 Blank and Max Value Address 05AA 500 783 ...
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... PIC18F8620 SUM(IDs) Boot/ SUM(8000:BFFF)+SUM(C000:FFFF)+(CFGW1L & 0000)+ Block1/ (CFGW1H & ...
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... EEPROM information must be included. An option to not include the data EEPROM information may be provided. When embedding data EEPROM information in the HEX file, it should start at address F00000h. Microchip Technology Inc. believes that this feature is important for the benefit of the end customer. 2010 Microchip Technology Inc. Checksum ...
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... LP, HS, HS/PLL, and XT modes only) OSC is the Power-up Timer Period, and T PWRT Conditions Normal programming V Bulk erase operations meet AC specifications s (Note s ; this can cause spurious program is the Oscillator Period. OSC 2010 Microchip Technology Inc. ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 2010 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...