ISD4003-04MSY

Manufacturer Part NumberISD4003-04MSY
DescriptionIC VOICE REC/PLAY 4MIN 28-SOIC
ManufacturerNuvoton Technology Corporation of America
SeriesISD4003
ISD4003-04MSY datasheet
 


Specifications of ISD4003-04MSY

InterfaceSPI/MicrowireFilter Pass Band3.4kHz
Duration4 MinMounting TypeSurface Mount
Package / Case28-SOIC (0.300", 7.50mm Width)Lead Free Status / RoHS StatusLead free / RoHS Compliant
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ISD4003 SERIES
ISD4003 SERIES
SINGLE-CHIP, MULTIPLE-MESSAGES
VOICE RECORD/PLAYBACK DEVICES
4-, 5-, 6-, AND 8-MINUTE DURATION
Publication Release Date: Oct 31, 2008
- 1 -
Revision 1.31

ISD4003-04MSY Summary of contents

  • Page 1

    ... ISD4003 SERIES SINGLE-CHIP, MULTIPLE-MESSAGES VOICE RECORD/PLAYBACK DEVICES 4-, 5-, 6-, AND 8-MINUTE DURATION - 1 - ISD4003 SERIES Publication Release Date: Oct 31, 2008 Revision 1.31 ...

  • Page 2

    ... Plastic Dual Inline Package (PDIP) .......................................................... 31 11.3. 28-Lead 8x13.4mm Plastic Thin Small Outline Package (TSOP) Type 1 - IQC ................. 32 11.4. 28-Lead 8x13.4mm Plastic Thin Small Outline Package (TSOP) Type 1 ........................... 33 11.5. Die Information .................................................................................................................... 34 12. ORDERING INFORMATION .......................................................................................................... 36 13. VERSION HISTORY ....................................................................................................................... 37 ISD4003 SERIES Publication Release Date: Oct 31, 2008 - 2 - Revision 1.31 ...

  • Page 3

    ... The CMOS-based devices include an on-chip oscillator, anti-aliasing filter, smoothing filter, AutoMute feature, audio amplifier, and high density multilevel Flash memory array. The ISD4003 series is designed to be used in a microprocessor- or microcontroller-based system. Address and control are accomplished through a Serial Peripheral Interface (SPI) or Microwire Serial Interface to minimize pin count ...

  • Page 4

    ... Available in die form, PDIP, SOIC, and TSOP • Packaged type: Lead-Free • Temperature: • Commercial (die): 0°C to +50°C - Commercial (packaged units): 0°C to +70°C - Industrial (packaged units): -40°C to +85°C - ISD4003 SERIES Publication Release Date: Oct 31, 2008 - 4 - Revision 1.31 ...

  • Page 5

    ... Sampling Clock 5-Pole Active Analog Transceivers Antialiasing Filter 1920K Cell Nonvolatile Multilevel Storage Array Device Control V V SCLK SS MOSI MISO INT SSD CCD - 5 - ISD4003 SERIES 5-Pole Active Smoothing Filter TM AutoMute Feature Amp AUDOUT RAC AM CAP Publication Release Date: Oct 31, 2008 Revision 1.31 ...

  • Page 6

    ... INT 5 XCLK CCD SCLK MOSI 10 MISO SSD ISD4003 SOIC / PDIP ISD4003 TSOP - 6 - ISD4003 SERIES SCLK V CCD XCLK INT RAC V SSA CCA ANA I N+ ANA CCA ANA IN+ 25 ANA IN CAP AUD OUT SSA V 17 SSA Publication Release Date: Oct 31, 2008 Revision 1.31 ...

  • Page 7

    ... Slave Select: This input, when LOW, will select the ISD4003 device. 10 Master Out Slave IN: This is the serial input to the ISD4003 device when it is configured as slave. The master microcontroller places data on the MOSI line one half-cycle before the rising edge of SCLK for clocking into the device. 11 Master In Slave Out: This is the serial output (open drain) of the ISD4003 device ...

  • Page 8

    ... In the differential-input mode, the maximum input signal at ANA IN+ should be 16 mVp-p capacitively coupled for optimal signal quality. The circuit connections for the two modes are shown in Figure ISD4003 SERIES FUNCTION .. CCA Publication Release Date: Oct 31, 2008 Revision 1.31 ...

  • Page 9

    ... INT Supply Voltage: To minimize noises, the analog and digital circuits in the ISD4003 devices use separate power busses. These +3V busses are brought out to separate pins and should be tied together as close to the supply as possible. In addition, these supplies should be decoupled as close to the package as possible. ...

  • Page 10

    ... The duty cycle on the input clock is not critical, as the clock is immediately divided by two. If the XCLK is not used, this input must be connected to ground. 8 Serial Clock : This is the input clock to the ISD4003 device generated by microcontoller) and is used to synchronize the data transfer in and out of the device through the MOSI and MISO lines, respectively ...

  • Page 11

    ... Input Signal 16m Vp-p Input Signal 16m Vp-p 180 ° μ 0.1 F Differential Input Mode FIGURE 1: ISD4003 SERIES ANA IN MODES RAC FIGURE 2: RAC TIMING WAVEFORM DURING NORMAL OPERATION Internal to the device 3K Ω ANA IN+ 3K Ω ANA IN- Internal to the device ANA IN+ 3K Ω ...

  • Page 12

    ... In addition, the device can be re- recorded typically over 100,000 times. Memory Architecture The ISD4003 series contains a total of 1,920K Flash memory cells, which is organized as 1,200 rows of 1,600 cells each. ® series is offered at 8.0, 6.4, 5.3 and 4.0 kHz sampling ...

  • Page 13

    ... SCLK signal, with LSB first. 4. Playback and record operations are initiated when the device is enabled by asserting the SS pin LOW, shifting in an opcode and an address data to the ISD4003 device (refer to the Opcode Summary in the following page). 5. The opcodes contain <11 address bits> and <5 control bits>. ...

  • Page 14

    ... Message Cueing can be selected only at the beginning of a playback operation. [2] As the Interrupt data is shifted out of the ISD4003, control and address data are being shifted in. Care should be taken such that the data shifted in is compatible with current system operation possible to read interrupt data and start a new operation at the same time ...

  • Page 15

    ... LSB MOSI A0 A1 Input Shift Register A0-A10 Row Counter P0-P10 Output Shift Register Message Cueing (MC) Ignore Address Bit (IAB) Power Up (PU) Play/Record (P/R) RUN FIGURE 4: SPI PORT - 15 - ISD4003 SERIES Select Logic P10 MSB A9 A10 Publication Release Date: Oct 31, 2008 Revision 1.31 ...

  • Page 16

    ... IAB should be changed before the end of that row (see RAC timing). Otherwise the ISD4003 will repeat the operation from the same row address. For memory management, the Row Address Clock (RAC) signal and IAB can be used to move around the memory segments. ...

  • Page 17

    ... In this mode, the messages are skipped 1,600 times faster than the normal playback mode. Power-Up Sequence The ISD4003 will be ready for an operation after power-up command is sent and followed by the T timing (25 ms for 8 KHz sampling rate). Refer to the AC timing table for other T to different sampling rates. ...

  • Page 18

    ... TIMING DIAGRAMS SS SCLK M OSI (TRISTATE) M ISO SS SCLK LSB A8 MOSI LSB OVF EOM MISO T SSS T T DIH SCKlow T DIS T PD LSB FIGURE 5: TIMING DIAGRAM A9 A10 FIGURE 6: 8-BIT COMMAND FORMAT - 18 - ISD4003 SERIES T SSH T SSm in T SCKhi Publication Release Date: Oct 31, 2008 Revision 1.31 ...

  • Page 19

    ... SCLK LSB MOSI LSB OVF EOM MISO FIGURE 7: 16-BIT COMMAND FORMAT SS SCLK MOSI Play/Record MISO Data ANA IN ANA OUT FIGURE 8: PLAYBACK/RECORD AND STOP CYCLE A10 Publication Release Date: Oct 31, 2008 - 19 - ISD4003 SERIES P10 Stop Data T STOP/PAUSE (Rec) T STOP/PAUSE (Play) Revision 1.31 ...

  • Page 20

    ... V – Note: Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum ratings may affect device reliability and performance. Functional operation is not implied at these conditions. ISD4003 SERIES 150°C -65°C to +150°C (V –0.3V –1.0V ...

  • Page 21

    ... TABLE 8: OPERATING CONDITIONS (DIE) CONDITIONS Commercial operating temperature range [1] Supply voltage ( [2] Ground voltage ( [ CCA CCD [ SSA SSD ISD4003 SERIES 0°C to +70°C -40°C to +85°C +2.7V to +3.3V 0V 0°C to +50°C +2.7V to +3.3V 0V Publication Release Date: Oct 31, 2008 - 21 - VALUES VALUES Revision 1.31 ...

  • Page 22

    ... OL1 0 EXT R 2.2 3.0 ANA IN ANA IN ARP = 25°C and V = 3.0V and all other pins floating. SSA SSA - 22 - ISD4003 SERIES [1] [2] MAX UNITS [3] [ µA ± 1 µ µA KΩ 3.8 KΩ 71 KΩ 32 mVpp 1 KHz dB sinewave input Publication Release Date: Oct 31, 2008 CONDITIONS = 10 µ ...

  • Page 23

    ... Publication Release Date: Oct 31, 2008 - 23 - ISD4003 SERIES [2] UNITS CONDITIONS [5] KHz [5] KHz [5] KHz [5] KHz [3][7] KHz 3 dB Roll-Off Point [3][7] KHz 3 dB Roll-Off Point [3][7] KHz 3 dB Roll-Off Point ...

  • Page 24

    ... For optimal signal quality, this maximum limit is recommended. [10] When a record command is sent, T [11] Measured with AutoMute feature disabled. = 3.0V and timing measurement at 50%. CC maximum for ANA IN+ and ANA IN the first row address. RAC RAC RACL Publication Release Date: Oct 31, 2008 - 24 - ISD4003 SERIES at 32 mVp-p. IN Revision 1.31 ...

  • Page 25

    ... SYMBOLS MIN TYP 0 OL1 0 THD A 23 ARP = 3.0V. Sampling Frequency can vary as much as ±2.25 percent = 25°C and and all other pins floating. SSA SSA - 25 - ISD4003 SERIES [1] [2] MAX UNITS [3] [ µ mVpp 1 KHz sinewave input dB 32 mVpp 1 KHz sinewave input ...

  • Page 26

    ... T 1 SSmin T 400 SCKhi T 400 SCKlow 3.0V and timing measurement at 50%. CC Ω MISO Ω 50pF (Includes scope and fixture capacitance ISD4003 SERIES [1] MAX UNITS CONDITIONS nsec nsec nsec nsec 500 nsec 500 nsec µsec nsec nsec 1,000 KHz Publication Release Date: Oct 31, 2008 ...

  • Page 27

    ... SSA SSA C11 SSA μ 0 ANA IN- AUD OUT ISD4003 25 24 C10 0.1 F μ ANA IN RAC CAP 25 INT μ XCLK PDIP / SOIC ISD4003 SERIES 0.22 F μ μ C3 0.22 F μ C4 μ 10K R4 R3 100 100K POT -IN GAIN-OUT 3 10 V01 14 + V02 5 5 BYPASS HP-IN1 ...

  • Page 28

    ... F μ ANA IN- AUD OUT ISD4003 C8 μ 0 ANA IN+ R1 10K 24 RAC 14 AM CAP C5 25 INT 1 F μ XCLK μ R5 4.7 K Ω Ω 4.7 K PDIP / SOIC - 28 - ISD4003 SERIES μ LINE OUT 100 100K POT -IN GAIN-OUT J4 3 V01 10 14 +IN 2 EXT 4 SPEAKER 15 V02 5 ...

  • Page 29

    ... F μ ANA IN- AUD OUT ISD4003 C8 μ 0 ANA IN+ R1 10K 24 RAC 14 AM CAP C5 25 INT 1 F μ XCLK μ R5 4.7 K Ω Ω 4.7 K PDIP / SOIC - 29 - ISD4003 SERIES μ LINE OUT 100 100K POT -IN GAIN-OUT J4 3 V01 10 14 +IN 2 EXT 4 SPEAKER 15 V02 5 ...

  • Page 30

    ... ISD4003 SERIES MILLIMETERS Nom Max 17.93 18.06 2.56 2.64 7.52 7.59 0.22 0.29 0.41 0.48 1.27 10.31 10.41 0.81 1.02 Publication Release Date: Oct 31, 2008 ...

  • Page 31

    ... ISD4003 SERIES MILLIMETERS Nom Max 36.83 36.96 3.81 1.78 1.91 15.88 13.72 13.97 4.83 3.43 0.46 0.56 1.52 1.62 2.54 0.25 0.30 1 ...

  • Page 32

    ... H 0.520 0.528 0.536 13.40 13. 0.022 L 0.50 0.020 0.024 0.028 L 1 0.031 Y 0.000 0.004 0.00 θ ISD4003 SERIES (TSOP IQC ACKAGE YPE 1.20 0.15 1.00 1.05 0.20 0.27 0.15 0.21 11.90 8.10 8.00 13.60 0.55 0.70 0.60 0.80 0.10 ...

  • Page 33

    ... Min 0.528 0.535 13.20 0.465 0.469 11.70 0.315 0.319 7.90 0.006 0.05 0.009 0.011 0.17 0.0217 0.039 0.041 0.95 3° 6° 0° 0.022 0.028 0.50 0.008 0. ISD4003 SERIES (TSOP ACKAGE YPE MILLIMETERS Nom Max 13.40 13.60 11.80 11.90 8.00 8.10 0.15 ...

  • Page 34

    ... NFORMATION ISD4003 Series Die Dimensions (with scribe line 166.6 ± 1 mils Y: 274.9 ± 1 mils [2] Die Thickness o 11.5 ± 0.5 mils Pad Opening o Single pad microns Double pad: 180 x 90 microns Notes: [1] The backside of die is internally connected to V damage may occur. [2] Die thickness is subject to change, please contact Nuvoton as this thickness may change in the future. ...

  • Page 35

    ... ANA IN- Inverting Analog Input ANA IN+ Noninverting Analog Input [1] V Analog Power Supply CCA [1] V Analog Power Supply CCA Note: [1] Double bond recommended if treated as one pad. ISD4003 SERIES P C ERIES AD OORDINATIONS X Axis (µm) 1885.2 1483.8 794.8 564.8 384.9 169.5 -14.7 -198.1 -1063.7 -1325 ...

  • Page 36

    ... Minutes Package Part # ISD4003-04MX I4304X Die ISD4003-04MPY I4304PY PDIP ISD4003-04MSY I4304SY SOIC ISD4003-04MSYI I4304SYI ISD4003-05MSYI ISD4003-04MEY I4304EY TSOP ISD4003-04MEYI I4304EYI ISD4003-05MEYI For the latest product information, access Nuvoton worldwide website at Packaged Units / Die : X = Die P = 28-Lead 600-mil Plastic Dual Inline Package (PDIP) ...

  • Page 37

    ... Remove the leaded package options Remove the extended temperature option Update the external clock description Revise Ordering Information section 1.31 Oct 31, 2008 Change logo. DESCRIPTION RACLO RACL parameter. ARP and V pin #. CCA CCD Publication Release Date: Oct 31, 2008 - 37 - ISD4003 SERIES Revision 1.31 ...

  • Page 38

    ... TEL: 1-408-9436666 FAX: 1-408-5441797 http://www.Nuvoton-usa.com/ Nuvoton Technology Corporation Japan 7F Daini-ueno BLDG. 3-7-18 Shinyokohama Kohokuku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 - 38 - ISD4003 SERIES ® ChipCorder ® ® and ISD are trademarks of Nuvoton Technology (Shanghai) Ltd. 27F, 299 Yan An W. Rd. Shanghai, 200336 China ...