ACPL-M71T-000E Avago Technologies US Inc., ACPL-M71T-000E Datasheet - Page 7

• Manufacturer Part Number: ACPL-M71T-000E
• Description: OPTOCOUPLER, LOGIC GATE, 3750VRMS
• Manufacturer: Avago Technologies US Inc.
• Series: R²Coupler™r

Specifications of ACPL-M71T-000E

• No. Of Channels: 1
• Optocoupler Output Type: Logic Gate
• Input Current: 15mA
• Output Voltage: 7V
• Opto Case Style: SOIC
• No. Of Pins: 5
• Isolation Voltage: 3.75kV
• Voltage - Isolation: 3750Vrms
• Number Of Channels: 1, Unidirectional
• Propagation Delay High - Low @ If: 26ns
• Current - Dc Forward (if): 15mA
• Input Type: DC
• Output Type: Push-Pull, Totem-Pole
• Mounting Type: Surface Mount
• Package / Case: 6-SOIC (0.173", 4.40mm Width) 5 Leads
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 516-2167-5; ACPL-M71T-000E

ACPL-M72T Low Power Mode Switching Specifications
Over recommended temperature (-40°C to +125°C), 3.0V ≤ V
Package Characteristics
All Typical at T
Notes:
1. t
2. PWD is defined as |t
3. t
4. CM
5. CM
7
Parameter
Propagation Delay Time to
Logic Low Output
Propagation Delay Time to
Logic High Output
Pulse Width Distortion
Propagation Delay Skew
Output Rise Time
(10% – 90%)
Output Fall Time
(90% - 10%)
Common Mode Transient
Immunity at Logic High
Output
Common Mode Transient
Immunity at Logic High
Output
Parameter
Input-Output Momentary
Withstand Voltage
Input-Output Resistance
Input-Output Capacitance
propagation delay is measured from the 50% (Vin or If ) on the falling edge of the input pulse to the 80% level of the rising edge of the V
recommended operating conditions.
PHL
PSK
H
L
is equal to the magnitude of the worst case difference in t
propagation delay is measured from the 50% (Vin or If ) on the rising edge of the input pulse to 0.8V on the falling edge of the V
is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state.
is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.
[4]
[5]
A
= 25°C.
[1]
[1]
PHL
[2]
- t
[3]
PLH
|.
Symbol
t
t
PWD
t
t
t
| CM
| CM
Symbol
V
R
C
PHL
PLH
PSK
R
F
ISO
I-O
I-O
H
L
|
|
Min.
25
25
Min.
4000
Typ.
60
35
25
10
10
40
40
PHL
Typ.
10
0.6
and/or t
Max.
100
100
50
60
14
DD
PLH
≤ 5.5V. All typical specifications at +25°C and VDD = 5V
Units
ns
ns
ns
ns
ns
ns
kV/Ps
kV/Ps
that will be seen between units at any given temperature within the
Max.
Test Conditions
I
Using Avago LED Driving
Circuit,
V
R
T
Using Avago LED Driving
Circuit,
V
R
F
A
2
2
IN
IN
=4mA, C
=25°C
=350:+/-5%, V
=350:, V
=0V, R
=4.5-5.5V, R
Units
V
:
pF
rms
1
L
=350:+/-5% ,
=15pF
CM
=1000V, T
1
=350:+/-5% ,
Test Conditions
RH ≤ 50%, t = 1 min.,
T
V
f = 1 MHz, T
CM
A
I-O
= 25°C
=1000V,
= 500 V dc
A
=25°C
A
= 25°C
Fig
7,8,
9,10,
14
15
16
O
signal. t
O
Note
1,2,3
4
5
signal.
PLH