AD9122-M5372-EBZ Analog Devices Inc, AD9122-M5372-EBZ Datasheet - Page 54

• Manufacturer Part Number: AD9122-M5372-EBZ
• Description: DAC Evaluation Board W/ ADL5372 Modulator
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9122-M5372-EBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: DAC
• Kit Application Type: Data Converter
• Silicon Core Number: AD9122
• Number Of Adc's: 2
• Number Of Bits: 16
• Sampling Rate (per Second): 1.2G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Power (typ) @ Conditions: 800mW @ 500MSPS
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9122, ADL5372
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9122
To maintain synchronization, the skew between the REFCLK
signals of the devices must be less than t
also a setup-and-hold time to be observed between the DCI and
data of each device and the REFCLK signal. When resetting the
FIFO, the FRAME signal must be held high for the time interval
required to write two complete input data words. A timing
diagram of the input signals is shown in Figure 83.
The preceding example shows a REFCLK frequency equal to
the data rate. While this is the most common situation, it is not
strictly required for proper synchronization. Any REFCLK
frequency that satisfies the following equation is acceptable.
where N = 0, 1, 2, or 3.
As an example, a configuration with 4× interpolation and clock
frequencies of f
200 MHz, and f
SYNCHRONIZATION WITH DIRECT CLOCKING
When directly sourcing the DAC sample rate clock, a separate
REFCLK input signal is required for synchronization. To
synchronize devices, the DACCLK signal and the REFCLK
signal must be distributed with low skew to all of the devices
being synchronized. If the devices need to be synchronized
f
SYNC_I
= f
DACCLK
VCO
SYNC_I
= 1600 MHz, f
/2
= 100 MHz is a viable solution.
N
and f
SYNC_I
REFCLKP(1)/
REFCLKP(2)/
REFCLKN(1)
REFCLKN(2)
RATE CLOCK
FRAMEP(2)/
FRAMEN(2)
≤ f
DACCLK
SAMPLE
CLOCK
SYNC
DCIP(2)/
DCIN(2)
DATA
FPGA
Figure 84. Typical Circuit Diagram for Synchronizing Devices to a System Clock
SKEW
= 800 MHz, f
nanoseconds. There is
Figure 83. Timing Diagram Required for Synchronizing Devices
CLOCK DRIVER
CLOCK DRIVER
LOW SKEW
LOW SKEW
t
SKEW
DATA
LENGTH TRACES
t
SU_DCI
=
MATCHED
Rev. A | Page 54 of 60
t
H_DCI
to a master clock, then use the master clock directly for generating
the REFCLK input (see Figure 84).
DATA RATE MODE SYNCHRONIZATION
The Procedure for Data Rate Synchronization when Directly
Sourcing the DAC Sampling Clock section outlines the steps
required to synchronize multiple devices in data rate mode. The
procedure assumes that the DACCLK and REFCLK signals are
applied to all of the devices. The procedure must be carried out
on each individual device.
Procedure for Data Rate Synchronization when Directly
Sourcing the DAC Sampling Clock
Configure for data rate, periodic synchronization by writing
0xC0 to the sync control register (Register 0x10). Additional
synchronization options are available and are described in the
Additional Synchronization Features section.
Poll the sync locked bit (Register 0x12, Bit 6) to verify that the
device is back-end synchronized. A high level on this bit indicates
that the clocks are running with a constant and known phase
relative to the sync signal.
Reset the FIFO by strobing the FRAME signal high for the time
interval required to input two complete data input words. Resetting
the FIFO ensures that the correct data is being read from the
FIFO of each of the devices simultaneously.
DACCLKP/
DACCLKN
REFCLKP/
REFCLKN
FRAMEP/
FREMEN
DCIP/
DCIN
DACCLKP/
DACCLKN
REFCLKP/
REFCLKN
FRAMEP/
FREMEN
DCIP/
DCIN
IOUT1P/
IOUT1N
IOUT2P/
IOUT2N