This notice is to inform you of a change that will be made to certain ADI products (see Material Report). Any issues with this PCN or
requirements to qualify the change (additional data or samples) must be sent to ADI within 30 days of publication date. ADI contact information
is listed below.
PCN Title:
Publication Date:
Effectivity Date:
Revision Description:
Description Of Change
Reason For Change
Initial Release
1)Correct power connect to 1.8V PMOS device.
2)EEPROM controller circuit was redesigned similar to AD9557.
3)Changed Power on Reset (POR) circuit to assert reset as soon as the 1.8V supply is applied to the digital core. POR is released after multiple
supplies are above 80% nominal threshold.
4)Updated Die id to reflect new revision code
5)Remove auto-clear logic in the sync distribution register.
6)Soft I/O UPDATE fixed so it only triggers when the LSB of register 0x0005 is set (1).
7)The truncated bits LSBs from the beta and gamma multipliers are tracked digitally enabling adjustments to ensure the steady-state solution
requires that the phases to be matched.
8)Altered IRQ generation circuitry to correct trigger identification.
9)Added 50pF bypass capacitance to VREG, and adding series resistance between charge pump and loop filter (~250 ohms), and between loop filter
and VCO tune input (~150 ohms) to improve phase noise performance.
10)Each profile has a new bit “Phase Lock Scale” in the first register byte (MSB bit) -- see register map version (3.0.0 or later). This selects a scale
for the phase lock threshold of nanoseconds (default is picoseconds).
1)Improve long term operation.
2)In order to reload the EEPROM following a chip reset, the user would have to perform a reset without loading the EEPROM first. This enables the
EEPROM to work as originally specified.
3)EEPROM intermittently corrupted at power on reset. Supply sequencing may cause improper part initialization. This enables the EEPROM to work
as specified
4)Die ID indicates new revision.
5)Sync distribution register also calibrates system clock edge. User was unable to synchronize distribution with software control bit without also
calibrating the system clock. This enables the sync function to work as originally intended
6)I2C soft I/O UPDATE is triggering when it shouldn’t. In the old die, I/O UPDATE triggers whether this bit is 0 or 1. This enables the Soft I/O Update
to work as specified
7)Loop Filter data precision error. Truncation of LSBs in beta and gamma multipliers causes loop instability for small phase errors. The incorrect loop
response allows any phase which results in no change in the average frequency to be a steady-state solution, meaning that one or more non-zero
phase difference might be misread as steady-state. This enables the device to function properly, as specified
8)If an IRQ capable event, such as "system clock calibration started", occurs prior to the relevant bit in the selection mask being set, the IRQ pin will
be asserted, but the status register will not indicate which event happened. The IRQ can only be cleared by clearing the specific event register, a
Product/Process Change Notice - PCN 10_0275 Rev. -
Analog Devices, Inc. Three T echnology Way Norwood, Massachusetts 02062-9106
AD9548 mask change
20-Oct-2010
11-Nov-2010 (the earliest date that a customer could expect to receive changed material)
Analog Devices, Inc. PCN 10_0275_Rev_- Page 1 of 4