603084 ABI, 603084 Datasheet - Page 2

• Manufacturer Part Number: 603084
• Description: ADAPTER, 16PIN, JEDEC SOIC C/S
• Manufacturer: ABI

Specifications of 603084

• Convert From: 16-SOIC
• Convert To: ISP JTAGMaster
• Svhc: No SVHC (18-Jun-2010)
• Ic Adapter Type: JEDEC SOIC
• Mounting Type: SMD
• Supported Devices: JTAGMaster
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

JTAGMaster - Quick and easy boundary scan testing
What is the JTAGMaster?
With older technologies, in-circuit testing is carried out by accessing the pins of a
device directly, usually using test clips. But with recent developments in electronics,
most PCB assemblies are highly populated and do not allow access to the pins of a
device, as is the case in BGA packages for instance.
The JTAGMaster gives you access to these devices that are bound to a JTAG chain
with the purpose of carrying out testing, fault-finding and even programming
operations. Boundary scan (or JTAG) is a widely recognised protocol implemented
in most modern Programmable Logic Devices (eg CPLDs, FPGAs) and requires
minimal hardware interface.
EXTEST Mode
This mode of testing, supported by the JTAGMaster, allows users
to gain control of the pins of devices on the chain. The state of
individual pins can be changed between output high or low and
the resulting effect can be traced and monitored on other pins.
The effect of changing pin states may be checked on the same
device or on other devices on the chain. It may also be traced on
components outside of the chain, using an instrument such as the
CircuitMaster 4000M for instance.
The JTAGMaster is aimed at the diagnosis and
debugging of complex PCB assemblies
containing
devices.
Using the boundary scan test protocol, pins of
each device can be individually
monitored to determine their functionality. This
operation can be carried out on static or active
boards over a pre-defined period of time.
Information from a board can be stored and
recalled by any user for simple verification of the
device(s) on a chain (with pass/fail results) or
deeper investigation using the graphical viewer
and zoom features. Analysing this information
can lead to the detection of :
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Automatic Functionality
Various automatic functions and access levels are available with JTAGMaster :
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(eg. open circuit/shorted pins)
Automatic Chain Detection reduces the time consuming process of identifying devices.
Automatic Training lets the software learn the status of the board by itself although manual intervention is also possible.
Automatic Data Comparison for quick evaluation with pass or fail results.
TestFlow Manager for easy to follow test sequences with data capture and report facility.
Manufacturing defects
Logic errors
Programme errors
Faults in external circuitry
(eg. pin failing to toggle/ faulty device)
(eg. incorrect/corrupted program)
(eg. missing or stuck input signal)
single or multiple embedded
and safely
BGA device in EXTEST mode with pin E15 set as Output Low.
Where is JTAGMaster?
Field Service Engineering
Production Engineering
Design Engineering
End of Line Testing
Devices in the chain can be bypassed
Test Engineering
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