CDB5461AU Cirrus Logic Inc, CDB5461AU Datasheet - Page 26

• Manufacturer Part Number: CDB5461AU
• Description: Eval Bd Sngl Phase Power/Energy
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5461AU

• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: CS5461A
• Primary Attributes: 1-Phase, Energy-to-Frequency Output
• Secondary Attributes: GUI, USB, SPI, Microwire Interfaces
• Processor To Be Evaluated: CS5461A, C8051F320
• Interface Type: USB
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1552

6. REGISTER DESCRIPTION
6.1 Configuration Register
26
PC[6:0]
Igain
EWA
Address: 0
Default = 0x000001
IMODE, IINV
EPP
EOP
EDP
ALT
VHPF (IHPF)
1.
2.
EWA
PC6
ALT
23
15
7
“Default” => bit status after power-on or reset
Any bit not labeled is Reserved. A zero should always be used when writing to one of these bits.
VHPF
PC5
22
14
ative to the current channel. When MCLK = 4.096 MHz and K = 1, the phase adjustment range
is approximately ±2.8 degrees with each step approximately 0.04 degrees (assuming a power
line frequency of 60 Hz). If (MCLK/K) is not 4.096 MHz, the values for the range and step size
should be scaled by the factor 4.096 MHz / (MCLK/K). Default setting is 0000000 = 0.0215 de-
gree phase delay at 60 Hz (when MCLK = 4.096 MHz).
0 = Gain is 10x (default)
1 = Gain is 50x
0 = Normal outputs (default)
10 = High-to-low pulse
1 = EOP and EDP bits defines the E1 and E2 pins.
0 = Logic level low (default)
quency proportional to the active power.
0 = High-pass filter disabled (default)
1 = High-pass filter enabled
Sets the gain of the current PGA.
Allows the E1 and E2 pins to be configured as open-collector output pins.
1 = Only the pull-down device of the E1 and E2 pins are active
Interrupt configuration bits. Select the desired pin behavior for indication of an interrupt.
00 = Active-low level (default)
01 = Active-high level
11 = Low-to-high pulse
Allows the E1 and E2 pins to be controlled by the EOP and EDP bits.
0 = Normal operation of the E1 and E2 pins. (default)
EOP defines the value of the E1 pin when EPP = 1.
0 = Logic level low (default)
Alternate pulse format, E1 and E2 becomes active low alternating pulses with an output fre-
0 = Normal (default), Mechanical Counter or Stepper Motor Format
1 = Alternate Pulse Format, also MECH = 1
Phase compensation. A 2’s complement number which sets a delay in the voltage channel rel-
EDP defines the value of the E2 pin when EPP = 1.
Enables the high-pass filter on the voltage (current) channel.
6
IHPF
PC4
21
13
5
IMODE
iCPU
PC3
20
12
4
PC2
IINV
K3
19
11
3
PC1
EPP
18
10
K2
2
EOP
PC0
K1
17
9
1
CS5461A
Igain
DS661F2
EDP
16
K0
8
0