MAX6955AAX Maxim Integrated Products, MAX6955AAX Datasheet - Page 7

• Manufacturer Part Number: MAX6955AAX
• Description: LED Drivers Integrated Circuits (ICs)
• Manufacturer: Maxim Integrated Products

Specifications of MAX6955AAX

• Number Of Digits: 16
• Number Of Segments: 128
• Low Level Output Current: 935000 uA
• High Level Output Current: 55000 uA
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Supply Current: 30000 uA
• Maximum Power Dissipation: 941 mW
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-36
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

serial clock line (SCL) to achieve bidirectional commu-
nication between master(s) and slave(s). A master (typ-
ically a microcontroller) initiates all data transfers to and
from the MAX6955, and generates the SCL clock that
synchronizes the data transfer (Figure 2).
The MAX6955 SDA line operates as both an input and
an open-drain output. A pullup resistor, typically 4.7kΩ,
is required on the SDA. The MAX6955 SCL line oper-
ates only as an input. A pullup resistor, typically 4.7kΩ,
is required on SCL if there are multiple masters on the
2-wire interface, or if the master in a single-master sys-
tem has an open-drain SCL output.
Each transmission consists of a START condition
(Figure 3) sent by a master, followed by the MAX6955
7-bit slave address plus R/W bit (Figure 4), a register
address byte, 1 or more data bytes, and finally a STOP
condition (Figure 3).
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning the SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 3).
Figure 1. Segment Labeling for 7-Segment Display, 14-Segment Display, and 16-Segment Display
Table 1. MAX6955 Drive Capability
DISPLAY TYPE
1f
1e
Monocolor
Bicolor
2-Wire Interfaced, 2.7V to 5.5V LED Display
1a
1g
1d
_______________________________________________________________________________________
1b
1c
Driver with I/O Expander and Key Scan
HEXADECIMAL FONT)
1dp
(16-CHARACTER
Start and Stop Conditions
7 SEGMENT
2f
2e
16
8
2d
2a
2g
2b
2c
2dp
(104-CHARACTER ASCII FONT MAP)
f
e
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable while SCL
is high (Figure 5).
The acknowledge bit is a clocked 9th bit that the recipient
uses to handshake receipt of each byte of data (Figure 6).
Thus, each byte transferred effectively requires 9 bits. The
master generates the 9th clock pulse, and the recipient
pulls down SDA during the acknowledge clock pulse, such
that the SDA line is stable low during the high period of the
clock pulse. When the master is transmitting to the
MAX6955, the MAX6955 generates the acknowledge bit
because the MAX6955 is the recipient. When the MAX6955
is transmitting to the master, the master generates the
acknowledge bit because the master is the recipient.
The MAX6955 has a 7-bit-long slave address (Figure
4). The eighth bit following the 7-bit slave address is the
R/W bit. It is low for a write command, high for a read
command.
The first 3 bits (MSBs) of the MAX6955 slave address
are always 110. Slave address bits A3, A2, A1, and A0
are selected by the address input pins AD1 and AD0.
These two input pins can be connected to GND, V+,
SDA, or SCL. The MAX6955 has 16 possible slave
addresses (Table 5) and therefore a maximum of 16
MAX6955 devices can share the same interface.
g1
m
h
14 SEGMENT/
16 SEGMENT
a
d
i
l
8
4
g2
k
j
b
c
dp
e
f
a1
d2
g1
m
h
(DIRECT CONTROL)
DISCRETE LEDs
i
l
d1
a2
g2
j
k
Slave Address
128
Acknowledge
64
Bit Transfer
b
c
dp
7