NCP1653ADR2G ON Semiconductor, NCP1653ADR2G Datasheet - Page 10

• Manufacturer Part Number: NCP1653ADR2G
• Description: IC PFC CONTROLLER CCM 8SOIC
• Manufacturer: ON Semiconductor

Specifications of NCP1653ADR2G

• Mode: Continuous Conduction (CCM)
• Frequency - Switching: 67kHz
• Voltage - Supply: 8.75 V ~ 18 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Switching Frequency: 67 KHz
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Startup: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: NCP1653ADR2G; NCP1653ADR2GOSTR

filter absorbs the high−frequency component of inductor
current I
signal only of the inductor current.
of the original I
From (eq.1) and (eq.2), the input impedance Z
formulated.
in (eq.3) is constant or slowly varying in the 50 or 60 Hz
bandwidth.
in Figure 27. The MOSFET on time t
intersection of reference voltage V
V
(eq.5). The multiplier voltage V
terms of t
Latch Reset
Figure 27. PFC Duty Modulation and Timing Diagram
V
ramp
The input filter capacitor C
The suffix 50 means it is with a 50 or 60 Hz bandwidth
Power factor is corrected when the input impedance Z
The PFC duty modulation and timing diagram is shown
The charging current I
M
Latch Set
C
Inductor
Current
filtering
ramp
without
Output
. A relationship in (eq.4) is obtained.
V
Clock
V
M
ramp
L
V
1
. It makes the input current I
ref
in (eq.6).
I
ch
V ramp + V M )
0
Z in +
L
.
I ch +
1
V in
I in + I L−50
I in
C ramp V ref
V
+
+
ch
M
T * t 1
filter
is specially designed as in
T
C ramp
V
T
clock
I ch t 1
V
M
ref
ramp
and the front−ended EMI
is therefore expressed in
PFC Modulation
−
+
I L−50
V out
ref
1
+ V ref
in
is generated by the
and ramp voltage
a low−frequency
R
S
http://onsemi.com
(eq.2)
(eq.3)
(eq.4)
(eq.5)
in
Q
is
in
10
re−formulated in (eq.7).
the multiplier voltage V
the I
It is illustrated in Figure 28.
originally consists of a switching frequency ripple coming
from the inductor current I
inaccurately generated due to this ripple. This modulation
is the so−called “peak current−mode”. Hence, an external
capacitor C
(Pin 5) is essential to bypass the high−frequency
component of V
“average current−mode” with a better accuracy for PFC.
(eq.8).
input voltage V
V M + V ref *
From (eq.3) and (eq.6), the input impedance Z
Because V
It can be seen in the timing diagram in Figure 27 that V
The multiplier voltage V
Input−voltage current I
V in
Figure 29. External Connection on the Multiplier
I L
V M
L−50
C
Figure 28. Multiplier Voltage Timing Diagram
M
I in
in order to have a constant Z
I
M
M
ref
connected to the multiplier voltage V
R
V
C ramp
and V
M
M
ac
M
. The modulation becomes the so−called
t 1
Z in +
V M +
as described in (eq.9). The suffix ac
5
out
C ramp V ref
Voltage Pin
M
are roughly constant versus time,
V ref
V M
R M I vac I S
vac
is designed to be proportional to
2 I control
T
M
I L−50
is proportional to the RMS
L
V out
. The duty ratio can be
is generated according to
+ V ref
V
in
M
=
for PFC purpose.
Modulation
T * t 1
PFC Duty
R
2I
T
M
control
I
vac
I
S
(eq.6)
(eq.7)
(eq.8)
M
time
time
time
in
pin
is
M