CDB61884 Cirrus Logic Inc, CDB61884 Datasheet
CDB61884
Specifications of CDB61884
Related parts for CDB61884
CDB61884 Summary of contents
Page 1
... CS61884-IQ CDB61884 This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright Cirrus Logic, Inc. 2002 © (All Rights Reserved) CDB61884 , E1 120 , or T1/J1 100 applications 120 or T1/J1 100 -40° to 85° C 144-pin LQFP Evaluation Board MAR ‘ ...
Page 2
... TABLE OF CONTENTS 1. CDB61884 EVALUATION BOARD LAYOUT .......................................................................... 4 2. BOARD COMPONENT DESCRIPTIONS ................................................................................. 5 2.1 Power Connections ............................................................................................................ 5 2.2 Master Clock Selection ...................................................................................................... 5 2.3 Operating Mode Selection ................................................................................................. 6 2.4 Line Interface Connections ................................................................................................ 6 2.5 TXOE Selection ................................................................................................................. 6 2.6 Clock Edge Selection ......................................................................................................... 7 2.7 Jitter Attenuator Selection .................................................................................................. 7 2.8 Loopback Mode Selection .................................................................................................. 7 2.9 Line Length Selection ........................................................................................................ 7 2 ...
Page 3
... Figure 6. Clock Edge Selection....................................................................................................... 7 Figure 7. Jitter Attenuator Selection................................................................................................ 7 Figure 8. Loopback Mode Selection................................................................................................ 7 Figure 9. Switch S9 Settings ........................................................................................................... 8 Figure 10. Digital Signal Control/Access......................................................................................... 9 Figure 11. CDB61884 Software Opening Screen ......................................................................... 10 Figure 12. Register Bit Box ........................................................................................................... 10 Figure 13. Set All Button ............................................................................................................... 10 Figure 14. Clear All Button ............................................................................................................ 11 Figure 15. Write All Button ............................................................................................................ 11 Figure 16. Read All Button ............................................................................................................ 11 Figure 17 ...
Page 4
... CDB61884 EVALUATION BOARD LAYOUT 1. Figure 1. CDB61884 Board Layout 4 CDB61884 DS485DB1 ...
Page 5
... A 1.544 MHz clock oscillator is also provided with the evaluation board for use as the on- board clock source for the T1/J1 operation modes. – A BNC connector (labeled J16) provides the connection for an external clock source. CDB61884 Figure 3 shows MCLK MCLK J1 On-board Oscillator ...
Page 6
... T1 and E1 Line Cards” (AN34REV1 SEP '94). 2.5 TXOE Selection E1 120 Jumper J23 is used to enable or High-Z all eight 15 transmitters in both hardware and host mode. A shorting block on Jumper J23 places all the trans- CDB61884 Table 2 are used to place or Table 2. To by- Table 2. Description Channel 0 RRING signal ...
Page 7
... Figure 8. Loopback Mode Selection 2.9 Line Length Selection In hardware mode, the transmit pulse shapes for 120 switches S12 through S14 (LEN 2-0). Refer to the Figure 7 CS61884 Data Sheet for the correct settings. CDB61884 S10 S10 HIGH HIGH OPEN OPEN LOW LOW ...
Page 8
... In host mode, switch S9 #2 (MUX) is used to select multiplex or non-multiplex. Placing switch MUX MOT_\INTL LO HI Hardware Mode - Enables HDB3/B8ZS coding & disables Channel 0 G.703 Bits Clock function Figure 9. Switch S9 Settings CDB61884 MUX MOT_\INTL LO HI Parallel Host Mode - Enables Motorola Non- Multiplex parallel host mode DS485DB1 ...
Page 9
... Switch S9 #1 and #2 are not used in Serial host mode. 4. HOST SOFTWARE INTERFACE The software provided with the CDB61884 evalu- ation board is used to control and monitor the CS61884 device. The program is designed to auto- matically read back each bit after each write. If the bit is read back incorrectly an error will occur ...
Page 10
... Figure 11. CDB61884 Software Opening Screen following registers do not have the automatic read back function: – AWG Phase Address – AWG Phase Data, – Software Reset registers. 4.1 Starting the Software There is no installation procedure associated with the CS61884 software, simply click on the appro- priate CS61884 software icon (95/98 or NT) on the CD in the CDB61884 kit ...
Page 11
... This button is located to the right of every register. reads ev- 4.6 Program Exit Function To exit any of the register screens simple press the X in the top right hand corner of each screen. This CDB61884 Figure 17 Figure 17. Write Button Figure 18 reads the bits Figure 18. Read Button writes ...
Page 12
... Click on the Read/ Write Registers button on the opening screen to start configuring these registers. 5.2.2 Select Register to Configure When the next screen appears, select the desired register screen by clicking on one of the TABs la- beled Loopback/Bits XMIT, AWG, or GCR at the top of the Read/Write Register screen. CDB61884 Clk, LOS/AIS/DFM, DS485DB1 ...
Page 13
... Loopback /Bits Clock Screen The Loopback /Bits Clock Register tabbed screen shown in isters: – Remote loop back – Analog loop back – Digital Loopback – G.703 Bits Clock Figure 20. Loopback/G.703 Bits Clock Selection Screen DS485DB1 CDB61884 Figure 20 allows access to the following reg- 13 ...
Page 14
... DFM interrupt Status – DFM Interrupt Enable – AIS Status – AIS Interrupt Enable – AIS Interrupt Status – JA Error Interrupt Enable – JA Error Interrupt Status . Figure 21. LOS/AIS/DFM/JA ERR Status/Enable Selection Screen 14 CDB61884 Figure 21 allows access to the following regis- DS485DB1 ...
Page 15
... Output Disable. Note: Some indictor boxes (bits) in the Performance Monitor, Line Length Channel ID, and Line Length Data registers are grayed out, this means that these bits can not be accessed. DS485DB1 Figure 22 consists of the following registers: Figure 22. Transmitter Register Screen CDB61884 15 ...
Page 16
... Chan Address input box. This is the same for every channel. The Chan Address, Sam- ple Address, and Phase Data input boxes use the values discussed in the AWG section of the CS61884 Data Sheet. 16 Figure 23 allows access to the following AWG registers: Figure 23. AWG Registers Screen CDB61884 DS485DB1 ...
Page 17
... Jitter Corner Freq. The variables listed above change the corresponding bit in the Global Control Register. The Software Re- set Register is a write only register and will clear after the write. The ID Register is a read only register. DS485DB1 Figure 24. Global Control Screen CDB61884 17 ...
Page 18
... BOARD CONFIGURATIONS 6 Mode Setup Table 4 shows the position of the different switches and jumpers used to set up the CDB61884 evaluation board to operate Hardware, Serial Host and Parallel Host operational modes. Before selecting Host mode, the switches in Table 4 Table Switches/Jumpers S15 (MODE) S1 (0) LOOP FUNCTION ...
Page 19
... E1 120 Mode Setup Table 5 shows the position of the different switches and jumpers used to set up the CDB61884 evaluation board to operate in E1 120 Hardware, Serial Host and Parallel Host operational modes. Before selecting host mode, the switches in Table 5 Table 5. E1 120 Switches/Jumpers ...
Page 20
... T1/J1 100 Mode Setup Table 6 shows the position of the different switches and jumpers used to set up the CDB61884 evaluation board to operate in T1/J1 100 lecting host mode the switches in Table 6. T1/J1 100 Switches/Jumpers S15 (MODE) S1 (0) LOOP FUNCTION S2 (1) LOOP FUNCTION S3 (2) ...
Page 21
... Before selecting any host mode place the CBLSEL, LOOP, ADDRESS, LEN and JASEL switches in the open or none position. – When using the CS61884 device in internal match impedance mode, be sure that the 1 K are not in series with the receivers. DS485DB1 CDB61884 resistors 21 ...
Page 22
...