CDB61880 Cirrus Logic Inc, CDB61880 Datasheet
CDB61880
Specifications of CDB61880
Related parts for CDB61880
CDB61880 Summary of contents
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... C CDB61880 This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright Cirrus Logic, Inc. 2002 (All Rights Reserved) CDB61880 in blue cross-references 144-pin LQFP Evaluation Board MAR ‘02 DS450DB1 ...
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... TABLE OF CONTENTS 1. CDB61880 EVALUATION BOARD LAYOUT .......................................................................... 4 2. BOARD COMPONENT DESCRIPTIONS ................................................................................. 5 2.1 Power Connections ............................................................................................................ 5 2.2 Master Clock Selection ...................................................................................................... 5 2.3 Operating Mode Selection ................................................................................................. 6 2.4 Line Interface Connections ................................................................................................ 6 2.5 TXOE Selection ................................................................................................................. 6 2.6 Clock Edge Selection ......................................................................................................... 7 2.7 Jitter Attenuator Selection .................................................................................................. 7 2.8 Loopback Mode Selection .................................................................................................. 7 2.9 Line Length/Impedance Selection ...................................................................................... 8 2 ...
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... BOARD CONFIGURATIONS ................................................................................................. 18 6 Ω Mode Setup ....................................................................................................... 18 6.2 E1 120 Ω Mode Setup ..................................................................................................... 19 7. EVALUATION HINTS ............................................................................................................. 20 LIST OF FIGURES Figure 1. CDB61880 Board Layout ................................................................................................. 4 Figure 2. On-board Logic Power Selection ..................................................................................... 5 Figure 3. Master Clock Selections .................................................................................................. 5 Figure 4. Hardware/Host Mode Selection ....................................................................................... 6 Figure 5. Transmitter Enable Selection........................................................................................... 7 Figure 6. Clock Edge Selection....................................................................................................... 7 Figure 7 ...
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... CDB61880 EVALUATION BOARD LAYOUT 1. 4 Figure 1. CDB61880 Board Layout CDB61880 DS450DB1 ...
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... BOARD COMPONENT DESCRIPTIONS 2.1 Power Connections Power for the CDB61880 evaluation board is sup- plied by an external +3 power supply power supply can also be connected to the on-board control logic. The LED labeled “D3” will illuminate when power is supplied to the on-board control logic. ...
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... TXOE Selection E1 120 Ω Ω Ω Ω Jumper J23 is used to enable or High-Z all eight 15Ω transmitters in both hardware and host mode. A shorting block on Jumper J23 places all the trans- CDB61880 Table 2 are used to place or Table Table 2. Table 2. Protection Resistor Selection ...
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... S1 through S8 (0-7). shows the three different settings for all eight loop back switches. In Host mode, switches S1 through S8 must be set to the NONE (middle) position to allow host inter- face control Hardware Mode - Selects Remote CDB61880 S10 S10 Hardware Mode Hardware Mode ...
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... Non-multiplex MOT_\INTL LO HI Hardware Mode - Enables HDB3/B8ZS coding & disables Channel 0 G.703 Bits Clock function Figure 9. Switch S9 Settings CDB61880 MOT_\INTL LO HI Parallel Host Mode - Enables Motorola Non- Multiplex parallel host mode DS450DB1 ...
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... S12 through S14 - Switches #1 and #2 inside of switch block S9 are used in Parallel Host mode to select Motorola, Intel, multiplex or Non-multiplex modes. Switch S9 #1 and #2 are not used in Serial Host mode. CDB61880 for switch S15 settings. Table 3. Switch Settings for Host Mode Switch Position NONE (middle) ...
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... Starting the Software There is no installation procedure associated with the CS61880 software, simply click on the appro- priate CS61880 software icon (Win95 or NT) on the CD in the CDB61880 kit. The CS61880 soft- ware is used to evaluate the CS61880 device. NOTE: The software can be used with Win- dows ® ...
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... Figure 16 reads ev- 4.6 Program Exit Function To exit any of the register screens simple press the X in the top right hand corner of each screen. This CDB61880 Figure 16. Read All Button Figure 17 writes the Figure 17. Write Button Figure 18 reads the bits Figure 18 ...
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... Click on the Read/ Write Registers button on the opening screen to start configuring these registers. 5.2.2 Select Register to Configure When the next screen appears, select the desired register screen by clicking on one of the TABs la- beled Loopback/Bits XMIT, AWG, or GCR at the top of the Read/Write Register screen. CDB61880 Clk, LOS/AIS/DFM, DS450DB1 ...
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... Loopback /Bits Clock Screen The Loopback /Bits Clock Register tabbed screen shown in Figure 20 allows access to the following registers: Figure 20. Loopback/G.703 Bits Clock Selection Screen DS450DB1 - Remote loop back - Analog loop back - Digital Loopback - G.703 Bits Clock CDB61880 13 ...
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... LOS Status - LOS Interrupt Enable - LOS Interrupt Status - LOS/AIS Mode Enable Figure 21. LOS/AIS/DFM/JA ERR Status/Enable Selection Screen 14 - DFM Status - DFM interrupt Status - DFM Interrupt Enable - AIS Status - AIS Interrupt Enable - AIS Interrupt Status - JA Error Interrupt Enable - JA Error Interrupt Status. CDB61880 DS450DB1 ...
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... DS450DB1 - Line Length Channel ID - Line Length Data - Output Disable. NOTE: Some indictor boxes (bits) in the Performance Monitor, Line Length Channel ID, and Line Length Data registers are grayed out, this means that these bits can not be accessed. Figure 22. Transmitter Register Screen CDB61880 15 ...
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... Chan Address input box. This is the same for every channel. The Chan Address, Sample Address, and Phase Data input boxes use the values discussed in the AWG section of the CS61880 Data Sheet. Figure 23. AWG Registers Screen CDB61880 DS450DB1 ...
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... Jitter Corner Freq. The variables listed above change the correspond- ing bit in the Global Control Register. The Soft- ware Reset Register is a write only register and will clear after the write. The ID Register is a read only register. Figure 24. Global Control Screen CDB61880 17 ...
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... BOARD CONFIGURATIONS 6 Ω Ω Ω Ω Mode Setup Table 4 shows the position of the different switches and jumpers used to set up the CDB61880 evalua- Table Ω Ω Ω Ω Operational Mode Switch/Jumper Position Switches/Jumpers S15 (MODE) S1 (0) S2 (1) S3 (2) S4 (3) S5 (4) S6 (5) S7 (6) ...
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... E1 120 Ω Ω Ω Ω Mode Setup Table 5 shows the position of the different switches and jumpers used to set up the CDB61880 evalua- tion board to operate in E1 120 Ω Hardware, Serial Table 5. E1 120 Ω Ω Ω Ω Operational Mode Switch/Jumper Position ...
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... Before selecting any Host mode place the CBLSEL, LOOP, ADDRESS and JASEL switches in the open or none position. - When using the CS61880 device in Internal Match Impedance mode, be sure that the 1 KΩ resistors are not in series with the receivers. CDB61880 DS450DB1 ...
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Notes • ...
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