LFE2-50E-D-EVN Lattice, LFE2-50E-D-EVN Datasheet
LFE2-50E-D-EVN
Specifications of LFE2-50E-D-EVN
Related parts for LFE2-50E-D-EVN
LFE2-50E-D-EVN Summary of contents
Page 1
... LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide June 2009 Revision: EB26_02.6 ...
Page 2
... Features • Lattice ECP2-50 FPGA with 48 kLUTs, 387 kbit of Embedded Block RAM, 18 sysDSP™ blocks, 72 18x18 multi- pliers, 6 PLLs, and 500 user I/O pins • Lattice MachXO™ with 640 LUTs and 6.1 kbit of RAM • ...
Page 3
... Related Literature • LatticeMico32 Development Kit User’s Guide : This guide includes a tutorial for using the LatticeMico32 Sys- tem software with the LatticeMico32/DSP Development Board. This document is written for the first generation board (with LatticeECP-33 FPGA), which is similar to the board described in this document ...
Page 4
... Lattice Semiconductor Overview The following block diagram gives you an overview of the functionality of your LatticeMico32/DSP Development Board. Subsequent pages illustrate the position of connectors, user interfaces, and modules. Figure 1. LatticeMico32/DSP Development Board Block Diagram PRG To PC Table 1. Board Defaults Item LatticeECP2-50 LCD Backlight (X5) Confi ...
Page 5
... Lattice Semiconductor Peripheral Interfaces This section describes all peripheral interfaces of the LatticeMico32/DSP Development Board for LatticeECP2 in alphabetical order. Figure 2 shows the position of peripheral interfaces available on the board. Figure 2. Peripheral Interfaces (Version 1 Board Shown in this Figure) Power Plug Connector 2.5V Testpoint 3.3V ...
Page 6
... A 25MHz oscillator supplies the FPGA (pin AD15), the CPLD (pin A8), the Ethernet controller and the Expansion Connector (pin 29 of X12). The frequency can be measured via testpoint CLK. To generate other clock frequencies use the PLLs of the FPGA. You can find detailed information on the usage of the PLLs on the Lattice website and in the LatticeECP2/M Family Data Sheet ...
Page 7
... DDR_BA0 Table 5. DDR SODIMM Socket (X4) - Other Signals Pin Signal Name 35 DDR_CK0+ 160 DDR_CK1+ 96 DDR_CKE0 118 DDR_RAS# 120 DDR_CAS# 122 DDR_S1# LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide FPGA Pin Pin Signal Name AE6 47 DDR_DQS2 AF6 48 DDR_DM2 AD9 41 DDR_DQ16 AD4 43 DDR_DQ17 Y5 ...
Page 8
... — 22 — 24 — 26 — 28 — 30 — 32 — 34 — for LatticeECP2 User’s Guide FPGA Pin N25 W25 Y26 R25 P26 R26 V26 V24 P25 W24 Signal Name FPGA Pin NC (coding) — EXPCON_IO29 H4 EXPCON_IO31 H6 EXPCON_IO33 H8 EXPCON_IO35 G2 EXPCON_IO37 G4 EXPCON_IO39 F2 EXPCON_IO41 F6 EXPCON_IO43 E2 EXPCON_IO45 E4 GND — ...
Page 9
... Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWN- LOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeECP2 FPGA device and render the board inoperable. ...
Page 10
... The LCD connector is a 16-pin header with a standard pinning for LCD modules with back-light (e.g. Truly MTC- C202DPRN-1N). In order to use an LCD module, attach it to the connector via a 16-pin ribbon cable. Note: The LCD module is tied supply. The LatticeECP2-50 to LCD interface is 3.3V. Put a jumper on connector X6 to turn on the backlight of the LCD. The contrast of the LCD module is adjustable with the potentiometer R0526, because different LCD modules need different voltages for the best contrast ...
Page 11
... Signal FPGA Pin RS_TXD_LVTTL K26 RS_RTS_LVTTL K25 RS_RXD_LVTTL J25 RS_CTS_LVTTL J26 FPGA Pin Pin AE20 93 AE13 91 AA20 89 AE19 86 11 for LatticeECP2 User’s Guide Signal Name FPGA Pin 2 SATA_X2D0 SATA_X2D0 SATA_X2D1 SATA_X2D1- W2 Direction RS232 Function Out Transmit Data Out Request to Send ...
Page 12
... PC. The CY7C68013A in combination with the MachXO CPLD acts as a built-in ispDOWNLOAD cable. The MachXO is connected to the ispDOWNLOAD Connector X3, and can program the LatticeECP2-50. The LatticeECP2-50 can be programmed when DIP switch SW0302 is ‘off’ (pushed down). Note: Like the ispDOWNLOAD connector, the MachXO drives the JTAG signals when it is programmed for USB confi ...
Page 13
... E13 40 F13 42 FPGA Pin Pin AF24 1 AF23 2 AF22 3 — 5 — 7 — 9 — 11 — 13 AF21 15 13 for LatticeECP2 User’s Guide Signal Name MachXO Pin GP_D15 N13 GP_ADR1 H2 GP_ADR3 J3 GP_ADR5 K2 GP_ADR7 L3 GP_SLOE M3 GP_INT1 M6 GP_FIFOADR1 N4 GP_PKTEND P5 USBCF_WAKE N9 GP_RDY1 E2 GP_RDY3 F3 GP_RDY5 G2 GP_CTL1 C3 GP_CTL3 C1 GP_CTL5 ...
Page 14
... Lattice Semiconductor Figure 4. VGA Connector LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide 14 ...
Page 15
... USB for Configuration LatticeMico32/DSP Development Board Audio Ethernet RS232 Line In 10/100M Connector Line Out LCD Sigma Delta Connector DAC Connector 15 for LatticeECP2 User’s Guide Mini USB VGA OTG Connector Connector USB Host Connector DDR SDRAM Sockel SATA LVDS Connectors Expansion Connector ...
Page 16
... Key Matrix The board also features a key matrix with 12 push-buttons, which are not debounced. They must be driven with three column lines and can be read with four rows. The following table shows the connections. LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide ...
Page 17
... This key is connected to a Schmitt trigger, meaning it is debounced. This key can be used as a single clock for test- ing your design. LatticeMico32/DSP Development Board TST_COL0 TST_COL1 FPGA Pin Signal Name H26 TST_COL0 H25 TST_COL1 H24 TST_COL2 H23 Col0 Col1 Col2 1 pressed 3 pressed Row0 6 pressed Row1 17 for LatticeECP2 User’s Guide TST_COL2 FPGA Pin G26 G25 G24 6 pressed ...
Page 18
... Figure 7. Components (Version 1 board Shown in this Figure) Ethernet PHY CPLD MachXO USB Configuration Controller LatticeMico32/DSP Development Board USB Host/ AC‘97 Audio Target/OTG Codec Controller SPI Reset Asynchronous Flash Controller SRAM 18 for LatticeECP2 User’s Guide FPGA LFEC250 Prototyping Area Parallel Flash ...
Page 19
... VCC3V3 TP0985 VCC3V3 TP09109 VCC3V3 TP0924 GND TP0948 GND TP0972 GND TP0996 GND TP09120 GND LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide FPGA Pin LRF Pin Signal Name A15 TP0902 BB3V3_IO1 C15 TP0904 BB3V3_IO3 A16 TP0906 BB3V3_IO5 E16 TP0908 BB3V3_IO7 ...
Page 20
... TP0936 TP0948 TP0960 TP0972 TP0984 TP0996 FPGA Pin SRAM Pin for LatticeECP2 User’s Guide BB3V3_IO[21:0] TP0997 TP09109 TP09121 TP09133 BB3V3_IO12 TP0998 TP09110 TP09122 TP09134 BB3V3_IO13 TP0999 TP09111 TP09123 TP09135 BB3V3_IO14 TP09100 TP09112 TP09124 TP09136 BB3V3_IO15 TP09101 TP09113 TP09125 TP09137 BB3V3_IO16 ...
Page 21
... USB ispDOWNLOAD cable. Using ispVM software the built-in download cable permits the FPGA, and SPI PROM programmed not recommended for the MachXO to be repro- grammed. However, the MachXO does provide some connections to the LatticeECP2-50 FPGA, and to an 8x6 pro- totyping area. ...
Page 22
... The ispLEVER design software can be used to develop/modify programs for the FPGA using Verilog or VHDL design entry methods. For more information on the ispLEVER software, see www.latticesemi.com/software. Sample programs for the FPGA are available on-line as well. These can be found at www.latticesemi.com/boards. Select FPGA/FPSC Boards -> LatticeMico32/DSP Development board for LatticeECP2 and click on the Design Files link ...
Page 23
... Lattice Semiconductor Note: The LatticeMico32/DSD Development Board generates byte enable outputs at the top-level HDL module. The board does not use these outputs, which causes ispLEVER to generate some warning messages. The warnings correctly tell the user that these pins are not connected or assigned to any location. The warnings can be avoided by either commenting out these byte enable outputs, or assigning them to unused I/O ...
Page 24
... Configure the SPI Flash as follows the ispVM System software, choose Edit -> Add Device to open the Device Information dialog box. 2. Click Select to open the Select Device dialog box. Select device family LatticeECP2, device LFE2-50E, and package 672 fpBGA from the drop-down lists. ...
Page 25
... Circuit diagrams for the localization of errors can be found in the appendix. Electrical Specifications Power requirement: regulated 5V DC Input current: 2000 mA Mechanical Specifications Dimensions: 160 mm [L] x 160 mm [ [H] Net weight: 160 g Temperature range LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide 2 C interface ...
Page 26
... JTAG_INIT PROGRAM# SISPI SPIDO SPIFASTN# DDR_A0 DDR_A1 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_A2 26 for LatticeECP2 User’s Guide Area 7-Segment Display 7-Segment Display 7-Segment Display 7-Segment Display 7-Segment Display 7-Segment Display 7-Segment Display 7-Segment Display 7-Segment Display 7-Segment Display AC97 Audio Codec ...
Page 27
... DDR_DQ2 DDR_DQ20 DDR_DQ21 DDR_DQ22 DDR_DQ23 DDR_DQ24 DDR_DQ25 DDR_DQ26 DDR_DQ27 DDR_DQ28 DDR_DQ29 DDR_DQ3 27 for LatticeECP2 User’s Guide Area DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM ...
Page 28
... ETH_RXD3 ETH_RXDV ETH_RXER ETH_TXCLK ETH_TXD0 ETH_TXD1 ETH_TXD2 ETH_TXD3 ETH_TXEN ETH_TXER CARDSEL# EXPCON_CLKIN 28 for LatticeECP2 User’s Guide Area DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM ...
Page 29
... EXPCON_IO37 EXPCON_IO38 EXPCON_IO39 EXPCON_IO4 EXPCON_IO40 EXPCON_IO41 EXPCON_IO42 EXPCON_IO43 EXPCON_IO44 EXPCON_IO45 EXPCON_IO5 EXPCON_IO6 29 for LatticeECP2 User’s Guide Area Expansion Connector Expansion Connector Expansion Connector Expansion Connector Expansion Connector Expansion Connector Expansion Connector Expansion Connector Expansion Connector Expansion Connector Expansion Connector Expansion Connector ...
Page 30
... MEMORY_A6 MEMORY_A7 MEMORY_A8 MEMORY_A9 MEMORY_DQ0 MEMORY_DQ1 MEMORY_DQ10 MEMORY_DQ11 MEMORY_DQ12 MEMORY_DQ13 MEMORY_DQ14 MEMORY_DQ15 MEMORY_DQ16 MEMORY_DQ17 MEMORY_DQ18 MEMORY_DQ19 30 for LatticeECP2 User’s Guide Area Expansion Connector Expansion Connector Expansion Connector Flash/SRAM Flash/SRAM Flash/SRAM Flash/SRAM Flash/SRAM Flash/SRAM Flash/SRAM Flash/SRAM Flash/SRAM Flash/SRAM Flash/SRAM Flash/SRAM Flash/SRAM ...
Page 31
... SRAM_CE# CLK_FPGA CLK_FPGA BB3V3_CLK0- BB3V3_CLK0+ BB3V3_IO0 BB3V3_IO1 BB3V3_IO10 BB3V3_IO11 BB3V3_IO12 BB3V3_IO13 BB3V3_IO14 BB3V3_IO15 BB3V3_IO16 BB3V3_IO17 BB3V3_IO18 BB3V3_IO19 BB3V3_IO2 31 for LatticeECP2 User’s Guide Area Flash/SRAM Flash/SRAM Flash/SRAM Flash/SRAM Flash/SRAM Flash/SRAM Flash/SRAM Flash/SRAM Flash/SRAM Flash/SRAM Flash/SRAM Flash/SRAM Flash/SRAM Flash/SRAM Flash/SRAM Flash/SRAM Flash/SRAM ...
Page 32
... MACHXO_IO12 MACHXO_IO13 MACHXO_IO14 MACHXO_IO15 MACHXO_IO2 MACHXO_IO3 MACHXO_IO4 MACHXO_IO5 MACHXO_IO6 32 for LatticeECP2 User’s Guide Area FPGA Prototyping Area FPGA Prototyping Area FPGA Prototyping Area FPGA Prototyping Area FPGA Prototyping Area FPGA Prototyping Area FPGA Prototyping Area FPGA Prototyping Area FPGA Prototyping Area ...
Page 33
... USB_GPIO15 USB_GPIO16 USB_GPIO17 USB_GPIO18 USB_GPIO19 USB_GPIO2 USB_GPIO20 USB_GPIO21 USB_GPIO22 USB_GPIO23 USB_GPIO24 USB_GPIO25 USB_GPIO26 USB_GPIO27 USB_GPIO28 USB_GPIO3 USB_GPIO4 USB_GPIO5 33 for LatticeECP2 User’s Guide Area MachXO MachXO MachXO Reset Reset RS232 RS232 RS232 RS232 SATA SATA SATA SATA SATA SATA SATA SATA ...
Page 34
... USB_SCK USB_SSI# USB_TXD VGA_BL0 VGA_BL1 VGA_GR0 VGA_GR1 VGA_HSYNC VGA_RD0 VGA_RD1 VGA_VSYNC Ordering Part Number LFE2-50E-D-EV 34 for LatticeECP2 User’s Guide Area USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface ...
Page 35
... February 2009 June 2009 © 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
Page 36
... Lattice Semiconductor Appendix A. Board Version 1 Schematic Figure 9. LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide ...
Page 37
... Lattice Semiconductor Figure 10 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide ...
Page 38
... Lattice Semiconductor Figure 11. Vcc 43 Vio 29 LatticeMico32/DSP Development Board Vss Vcc Vss Vss Vio Vss for LatticeECP2 User’s Guide ...
Page 39
... Lattice Semiconductor Figure 12 LatticeMico32/DSP Development Board TST_COL2 TST_COL1 TST_COL0 C. SEG_CA0# C. SEG_CA1#_X 39 for LatticeECP2 User’s Guide ...
Page 40
... Lattice Semiconductor Figure 13 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide ...
Page 41
... Lattice Semiconductor Figure 14. LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide 2 2 ...
Page 42
... Lattice Semiconductor Figure 15 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide ...
Page 43
... Lattice Semiconductor Figure 16 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide ...
Page 44
... Lattice Semiconductor Figure 17 LatticeMico32/DSP Development Board + + + for LatticeECP2 User’s Guide ...
Page 45
... Lattice Semiconductor Figure 18 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide ...
Page 46
... Lattice Semiconductor Appendix B. Board Version 2 Schematic Figure 19. LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide 46 ...
Page 47
... Lattice Semiconductor Figure 20. LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide ...
Page 48
... Lattice Semiconductor Figure 21 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide ...
Page 49
... Lattice Semiconductor Figure 22. Vcc 43 Vio 29 LatticeMico32/DSP Development Board Vss Vcc Vss 52 43 Vss Vio Vss for LatticeECP2 User’s Guide ...
Page 50
... Lattice Semiconductor Figure 23. TST_COL2 5 3 TST_COL1 TST_COL0 LatticeMico32/DSP Development Board C. SEG_CA0# SEG_CA1# for LatticeECP2 User’s Guide ...
Page 51
... Lattice Semiconductor Figure 24 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide ...
Page 52
... Lattice Semiconductor Figure 25. LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide ...
Page 53
... Lattice Semiconductor Figure 26 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide ...
Page 54
... Lattice Semiconductor Figure 27 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide ...
Page 55
... Lattice Semiconductor Figure 28 LatticeMico32/DSP Development Board + + for LatticeECP2 User’s Guide ...
Page 56
... Lattice Semiconductor Figure 29 LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide ...
Page 57
... Lattice Semiconductor Figure 30. LatticeMico32/DSP Development Board for LatticeECP2 User’s Guide 57 ...