CS495303-CVZ Cirrus Logic Inc, CS495303-CVZ Datasheet
CS495303-CVZ
Specifications of CS495303-CVZ
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CS495303-CVZ Summary of contents
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FEATURES Multi-standard 32-bit Audio Decoding plus Post Processing ™ Framework Applications Library in ROM ® ® — Dolby Digital EX, Dolby Pro Logic ® ® Dolby Virtual Speaker ™ ™ — DTS-ES 96/24 , DTS-ES Discrete 6.1, DTS-ES ™ DTS:Neo6 ...
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CS4953xx Data Sheet 32-bit Audio Decoder DSP Family Table of Contents 1. Documentation Strategy ...........................................................................................................4 2. Overview ....................................................................................................................................4 2.1 Migrating from the CS495xx(2) to the CS4953xx ..................................................................................... 4 2.2 Licensing .................................................................................................................................................. 4 3. Code Overlays ...........................................................................................................................5 4. Hardware Functional Description ...
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... Figure 24. 144-Pin LQFP Package Drawing .........................................................................................................35 List of Tables Table 1. CS4953xx Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 2. Device and Firmware Selection Guide Table 3. CS495303 DSP Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4. CS495313 DSP Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 6. Environmental, Manufacturing, & Handling Information Table 7. 128-Pin LQFP Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 8 ...
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... There are two devices in the CS4953xx DSP family. The CS495303 and CS495313 are differentiated by internal memory size and DSP Firmware. The CS495303 is available in a 128-pin QFP package and the CS495313 is available in either a 128-pin or 144-pin QFP package. The audio processing features of the CS495313 are a superset of audio features available in the CS495303 ...
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Code Overlays The suite of software available for the CS4953xx family consists of an operating system (OS) and a library of overlays. The overlays have been divided into three main groups called Decoders, Mid-processors, and Post- processors. All software ...
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... More features may now be available. Check with your Cirrus Logic Field Application Engineer (FAE) to obtain the latest feature list for the CS495303 and CS495313 products. ...
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... Modulo and linear addressing modes are supported, with flexible start address and increment controls. The service interval for each DMA channel as well interrupt events, is programmable. DS705PP2 Table 3. CS495303 DSP Memory Sizes DSP A 16k SRAM, 16k ROM 10k SRAM, 8k ROM ...
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CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 4.2 On-chip DSP Peripherals 4.2.1 Digital Audio Input Port (DAI) The 12-channel (6 line) DAI port supports a wide variety of data input formats. The port is capable of accepting PCM, IEC61937, ...
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DSP I/O Description 4.3.1 Multiplexed Pins Many of the CS4953xx pins are multi-functional. For details on pin functionality please refer to the CS4953xx Hardware User’s Manual. 4.3.2 Termination Requirements Open-drain pins on the CS4953xx must be pulled high for ...
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CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5. Characteristics and Specifications Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and temperature. All data sheet typical parameters are measured under the following conditions: ...
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Power Supply Characteristics (measurements performed under operating conditions) Parameter Power supply current: 1 Core and I/O operating: VDD PLL operating: VDDA With external memory and most ports operating: VDDIO 1. Dependent on application firmware and DSP clock speed. 5.5 ...
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CS4953xx Data Sheet 32-bit Audio Decoder DSP Family RESET# All Bidirectional 5.8 Switching Characteristics — XTI Parameter 1 External Crystal operating frequency XTI period XTI high time XTI low time External Crystal Load Capacitance (parallel resonant) External Crystal Equivalent Series ...
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Switching Characteristics — Internal Clock Parameter 1 Internal DCLK frequency 1 Internal DCLK period 1. After initial power-on reset, F dclk locked until the next power-on reset. DS705PP2 Symbol F dclk CS49530x-CVZ CS49531x-CQZ CS49531x-CVZ CS49530x-DVZ CS49531x-DQZ CS49531x-DVZ DCLKP CS49530x-CVZ ...
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CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.10 Switching Characteristics — Serial Control Port - SPI Slave Mode Parameter 1 SCP_CLK frequency SCP_CS# falling to SCP_CLK rising SCP_CLK low time SCP_CLK high time Setup time SCP_MOSI input Hold time ...
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Switching Characteristics — Serial Control Port - SPI Master Mode Parameter 1 SCP_CLK frequency 3 SCP_CS# falling to SCP_CLK rising SCP_CLK low time SCP_CLK high time Setup time SCP_MISO input Hold time SCP_MISO input SCP_CLK low to SCP_MOSI output ...
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CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.12 Switching Characteristics — Serial Control Port - I Parameter 1 SCP_CLK frequency SCP_CLK low time SCP_CLK high time SCP_SCK rising to SCP_SDA rising or falling for START or STOP condition START ...
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Switching Characteristics — Serial Control Port - I Parameter 1 SCP_CLK frequency SCP_CLK low time SCP_CLK high time SCP_SCK rising to SCP_SDA rising or falling for START or STOP condition START condition to SCP_CLK falling SCP_CLK falling to STOP ...
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CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.14 Switching Characteristics — Parallel Control Port - Intel Parameter Address setup before PCP_CS# and PCP_RD# low or PCP_CS# and PCP_WR# low Address hold time after PCP_CS# and PCP_RD# low or PCP_CS# ...
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PCP_A[3:0] t iah PCP_D[7:0] t ias PCP_CS# t icdr PCP_WR# PCP_RD# PCP_IRQ# Figure 7. Parallel Control Port - Intel PCP_A[3:0] t iah PCP_D[7:0] t ias PCP_CS# t icdw PCP_RD# PCP_WR# PCP_BSY# Figure 8. Parallel Control Port - Intel Mode Write ...
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CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.15 Switching Characteristics — Parallel Control Port - Motorola Parameter Address setup before PCP_CS# and PCP_DS# low Address hold time after PCP_CS# and PCP_DS# low Read Delay between PCP_DS# then PCP_CS# low ...
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HADDR[3:0] t mas HDATA[7:0] HEN t mrwsu HR/W HDS HREQ Figure 9. Parallel Control Port - Motorola HADDR[3:0] t mas HDATA[7:0] HEN HR/W HDS HREQ Figure 10. Parallel Control Port - Motorola Mode Write Cycle Timing DS705PP2 t mah LSP ...
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CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.16 Switching Characteristics — UART Parameter 1 UART_CLK period UART_CLK duty cycle Setup time for UART_RXD Hold time for UART_RXD Delay from CLK transition to TXD transition 1. The minimum clock period ...
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Switching Characteristics — Digital Audio Slave Input Port Parameter DAI_SCLK period DAI_SCLK duty cycle Setup time DAI_DATAn Hold time DAI_DATAn DAI_SCLK DAI_DATAn Figure 12. Digital Audio Input (DAI) Port Timing Diagram DS705PP2 Symbol T t daidsu ®Copyright 2008 Cirrus ...
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CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.18 Switching Characteristics — DSD Slave Input Port Parameter DSD_SCLK Pulse Width Low DSD_SCLK Pulse Width High DSD_SCLK Frequency DSD_A / _B valid to DSD_SCLK rising setup time DSD_SCLK rising to DSD_A ...
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DAO_MCLK DAO_SCLK DAO_DATAn DAO_LRCLK Figure 14. Digital Audio Port Timing, MCLK Master Mode DS705PP2 T daomclk t daomsck daomdv daosdv t daomstlr ®Copyright 2008 Cirrus Logic, Inc. CS4953xx Data Sheet 32-bit Audio Decoder DSP Family t daomstlr ...
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CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.20 Switching Characteristics — External Memory Interface - Flash Mode Parameter Write Cycle Address Setup time to EXT_WE# falling 1 EXT_CS# falling to EXT_WE# falling 1 EXT_CS# falling to EXT_WE# rising EXT_WE# ...
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EX T_A [19:0] EX T_C S1# EX T_C S2# E XT_W T_D [15:0] Figure 15. External Memory Interface - Flash Write Cycle Timing EXT_A[19:0] EXT_CS1# EXT_CS2# EXT_OE# EXT_D[15:0] Figure 16. External Memory Interface - Flash Read Cycle ...
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CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.21 Switching Characteristics — SDRAM Interface Refer to Figure 17 through Figure (SD_CLKOUT = SD_CLKIN) Parameter SD_CLKIN high time SD_CLKIN low time SD_CLKOUT rise/fall time SD_CLKOUT Frequency SD_CLKOUT duty cycle SD_CLKOUT rising ...
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SD_CLKOUT t t sdcmdv sdcmdh SD_CS# SD_RAS# SD_CAS# SD_WE# t sddqv SD_DQMn SD_An t sdav t sddsu CAS=2 SD_Dn SD_CLKIN t sdclkl Figure 17. External Memory Interface - SDRAM Burst Read Cycle SD_CLKOUT t t sdcmdv sdcmdh SD_CS# SD_RAS# SD_CAS# ...
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CS4953xx Data Sheet 32-bit Audio Decoder DSP Family SD_CLKOUT t sdcmdv SD_CS SD_RAS SD_CAS SD_WE SD_DQMn SD_ADDRn SD_DATAn Figure 19. External Memory Interface - SDRAM Auto Refresh Cycle SD_CLKOUT t sdcmdv SD_CS SD_RAS SD_CAS SD_WE SD_DQMn SD_ADDRn SD_DATAn Figure 20. ...
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... CS495313-DQZ CS495313-CVZ CS495313-DVZ Note: Please contact the factory for availability of the -D (automotive grade) package. 7. Environmental, Manufacturing, & Handling Information Table 6. Environmental, Manufacturing, & Handling Information Model Number CS495303-CVZ CS495303-DVZ CS495313-CQZ CS495313-DQZ CS495313-CVZ CS495313-DVZ * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. DS705PP2 Table 5 ...
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CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 8. Device Pinout Diagrams 8.1 128-Pin LQFP Pinout Diagram GPIO38, PCP_WR# / DS#, SCP2_CLK GPIO11, PCP_A3, AS#, SCP2_MISO / SDA GPIO10, PCP_A2 / A10, SCP2_MOSI GPOI9, SCP1_IRQ# GPIO8, PCP_IRQ#, SCP2_IRQ# GPIO7, SCP1_CS#, ...
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LQFP Pinout Diagram 109 GPIO9, PCP_A1 / A9 GPIO8, PCP_A0 / A8 110 GPIO7, PCP_AD7 / D7 GPIO6, PCP_AD6 / D6 VDDIO7 113 GPIO5, PCP_AD5 / D5 115 GPIO4, PCP_AD4 / D4 GNDIO7 116 GPIO3, PCP_AD3 / D3 ...
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CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 9. Package Mechanical Drawings 9.1 128-pin LQFP Package Drawing ∝ L DIM MIN A --- A1 0. 0° L 0.45 ...
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LQFP Package D D1 Notes: 1. Controlling dimension is millimeter. 2. Dimensioning and tolerancing per ASME Y14.5M- 1994. DIM MIN A --- A1 0. 0° L 0.45 L1 ddd DS705PP2 ...
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CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 10. Revision History Revision Date A1 FEB 2006 Advance release. A2 JUN 2006 Updated part numbers for ordering (Tables 5 & 6), Updated V include the current load used for testing A3 ...
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Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com. IMPORTANT NOTICE “Preliminary” product information describes products that are in production, but for which ...
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CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 38 ®Copyright 2008 Cirrus Logic, Inc. DS705PP2 ...