CY62157EV30LL-45ZSXIT Cypress Semiconductor Corp, CY62157EV30LL-45ZSXIT Datasheet - Page 9

• Manufacturer Part Number: CY62157EV30LL-45ZSXIT
• Description: CY62157EV30LL-45ZSXIT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY62157EV30LL-45ZSXIT

• Format - Memory: RAM
• Memory Type: SRAM
• Memory Size: 8M (512K x 16)
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TSOP II
• Memory Configuration: 512K X 16
• Access Time: 45ns
• Supply Voltage Range: 2.2V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 44
• Operating Temperature Range: -40°C To +85°C
• Density: 8Mb
• Access Time (max): 45ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 2.5/3.3V
• Address Bus: 19b
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 25mA
• Operating Supply Voltage (min): 2.2V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Word Size: 16b
• Number Of Words: 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Waveforms
Notes
Document #: 38-05445 Rev. *H
Figure 8
Figure 9
23. The internal write time of the memory is defined by the overlap of WE, CE = V
24. Data I/O is high impedance if OE = V
25. If CE
26. During this period, the I/Os are in output state. Do not apply input signals.
write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
ADDRESS
ADDRESS
BHE/BLE
BHE/BLE
DATA I/O
DATA I/O
1
goes HIGH and CE
shows WE Controlled write cycle waveforms.
shows CE
CE
CE
CE
CE
WE
WE
OE
OE
1
2
1
2
NOTE 26
NOTE 26
1
or CE
2
goes LOW simultaneously with WE = V
2
Controlled write cycle waveforms.
(continued)
IH
t
.
SA
t
t
HZOE
HZOE
t
SA
Figure 8. Write Cycle No. 1
Figure 9. Write Cycle No. 1
t
t
AW
AW
[23, 24, 25]
IH
, the output remains in a high impedance state.
t
SCE
t
t
WC
WC
[23, 24, 25]
IL
, BHE, BLE or both = V
t
t
BW
BW
VALID DATA
VALID DATA
t
t
t
t
PWE
PWE
SD
SD
t
SCE
IL
, and CE
2
t
t
HD
HD
= V
t
t
CY62157EV30 MoBL
HA
HA
IH
. All signals must be active to initiate a
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