24LC025T-E/OT Microchip Technology, 24LC025T-E/OT Datasheet - Page 5

• Manufacturer Part Number: 24LC025T-E/OT
• Description: 2K, 256 X 8 SERIAL EE, EXT 6 SOT-23 4.4mm T/R
• Manufacturer: Microchip Technology

Specifications of 24LC025T-E/OT

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2K (256 x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: SOT-23-6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.0
Pin Function Table
2.1
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open-drain
terminal; therefore, the SDA bus requires a pull-up
resistor to V
400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.2
The SCL input is used to synchronize the data transfer
from and to the device.
2.3
The levels on the A0, A1 and A2 inputs are compared
with the corresponding bits in the slave address. The
chip is selected if the compare is true. For the SOT-23
package only, pin A2 is not connected.
Up to eight 24AA024/24LC024/24AA025/24LC025
devices (four for the SOT-23 package) may be con-
nected to the same bus by using different Chip Select
bit combinations. These inputs must be connected to
either V
2.4
WP is the hardware write-protect pin. It must be tied to
V
enabled. If WP is tied to Vss, the hardware write
protection is disabled. Note that the WP pin is available
only on the 24XX024. This pin is not internally
connected on the 24LC025.
© 2009 Microchip Technology Inc.
CC
Name
SDA
SCL
V
V
WP
A0
A1
A2
or V
CC
SS
CC
SS
PIN DESCRIPTIONS
SDA Serial Data
SCL Serial Clock
A0, A1, A2
WP (24XX024 Only)
or V
. If tied to Vcc, hardware write protection is
CC
PDIP
SS
(typical 10 kΩ for 100 kHz, 2 kΩ for
1
2
3
4
5
6
7
8
.
24AA024/24LC024/24AA025/24LC025
SOIC
1
2
3
4
5
6
7
8
TSSOP
1
2
3
4
5
6
7
8
DFN/TDFN
1
2
3
4
5
6
7
8
2.5
The 24AA024/24LC024/24AA025/24LC025 employs a
V
internal erase/write logic if the V
nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
3.0
The 24AA024/24LC024/24AA025/24LC025 supports
a bidirectional, 2-wire bus and data transmission
defined as transmitter, while a device receiving data
is defined as receiver. The bus has to be controlled
by a master device that generates the Serial Clock
(SCL), controls the bus access and generates the
Start and Stop conditions, while the 24AA024/
24LC024/24AA025/24LC025 works as slave. Both
master and slave can operate as transmitter or
receiver, but the master device determines which
mode is activated.
protocol. A device that sends data onto the bus is
MSOP
CC
1
2
3
4
5
6
7
8
threshold detector circuit which disables the
Noise Protection
FUNCTIONAL DESCRIPTION
SOT-23
—
—
5
4
2
3
1
6
Address Pin AO
Address Pin A1
Address Pin A2
Ground
Serial Address/Data I/O
Serial Clock
Write-Protect Input
+1.7 to 5.5V Power Supply
Description
CC
is below 1.5V at
DS21210N-page 5