25LC640AXT-E/ST Microchip Technology, 25LC640AXT-E/ST Datasheet - Page 11

• Manufacturer Part Number: 25LC640AXT-E/ST
• Description: 64K, 8K X 8, 2.5V SER EE EXT, ROTATED PINOUT 8 TSSOP 4.4mm T/R
• Manufacturer: Microchip Technology

Specifications of 25LC640AXT-E/ST

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 64K (8K x 8)
• Speed: 10MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 25LC640AXT-E/STTR

2.6
The Write Status Register instruction (WRSR) allows the
user to write to the nonvolatile bits in the STATUS reg-
ister as shown in Table 2-2. The user is able to select
one of four levels of protection for the array by writing
to the appropriate bits in the STATUS register. The
array is divided up into four segments. The user has the
ability to write-protect none, one, two, or all four of the
segments of the array. The partitioning is controlled as
shown in Table 2-3.
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP pin. The
Write-Protect (WP) pin and the Write-Protect Enable
(WPEN) bit in the STATUS register control the
programmable hardware write-protect feature. Hard-
ware write protection is enabled when WP pin is low
and the WPEN bit is high. Hardware write protection is
disabled when either the WP pin is high or the WPEN
bit is low. When the chip is hardware write-protected,
only writes to nonvolatile bits in the STATUS register
are disabled. See Table 2-4 for a matrix of functionality
on the WPEN bit.
FIGURE 2-7:
© 2008 Microchip Technology Inc.
SCK
Note:
CS
SO
SI
Write Status Register Instruction
(WRSR)
An internal write cycle (T
sequence.
0
0
WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
0
1
0
Instruction
2
0
3
WC
0
) is initiated on the rising edge of CS after a valid write STATUS register
4
0
5
High-Impedance
0
6
1
7
25AA640A/25LC640A
See Figure 2-7 for the WRSR timing sequence.
TABLE 2-3:
7
8
BP1
0
0
1
1
6
9
Data to STATUS Register
10
5
11
4
ARRAY PROTECTION
BP0
0
1
0
1
12
3
13
2
Array Addresses
Write-Protected
(1800h-1FFFh)
(1000h-1FFFh)
(0000h-1FFFh)
14
upper 1/4
upper 1/2
1
DS21830D-page 11
none
all
15
0