AD5243BRMZ100-RL7 Analog Devices Inc, AD5243BRMZ100-RL7 Datasheet - Page 18

• Manufacturer Part Number: AD5243BRMZ100-RL7
• Description: IC,Digital Potentiometer,TSSOP,10PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD5243BRMZ100-RL7

• Taps: 256
• Resistance (ohms): 100K
• Number Of Circuits: 2
• Temperature Coefficient: 35 ppm/°C Typical
• Memory Type: Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resistance In Ohms: 100K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD5243EVAL - BOARD EVAL FOR AD5243
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5243/AD5248
I
Write Bit Patterns
Read Bit Patterns
Multiple Devices on One Bus (Applies Only to AD5248)
Figure 50 shows four AD5248 devices on the same serial bus.
Each has a different slave address because the states of their
AD0 and AD1 pins are different. This allows each device on the
bus to be written to or read from independently. The master
device output bus line drivers are open-drain pull-downs in a
fully I
2
C CONTROLLER PROGRAMMING
2
START BY
MASTER
START BY
MASTER
C-compatible interface.
SCL
SDA
SCL
SDA
1
1
0
0
SLAVE ADDRESS BYTE
SLAVE ADDRESS BYTE
START BY
MASTER
START BY
MASTER
1
1
FRAME 1
FRAME 1
0
0
SCL
SDA
SCL
SDA
Figure 48. Reading Data from a Previously Selected RDAC Register in Write Mode—AD5243
Figure 49. Reading Data from a Previously Selected RDAC Register in Write Mode—AD5248
1
1
1
1
1
0
1
0
SLAVE ADDRESS BYTE
SLAVE ADDRESS BYTE
AD1 AD0
1
1
1
1
FRAME 1
FRAME 1
0
0
R/W
R/W
Figure 46. Writing to the RDAC Register—AD5243
Figure 47. Writing to the RDAC Register—AD5248
1
1
ACK BY
AD5243
ACK BY
AD5248
9
9
1
1
A0
A0
AD1 AD0
1
1
1
SD
SD
1
Rev. A | Page 18 of 20
INSTRUCTION BYTE
INSTRUCTION BYTE
R/W
R/W
X
X
ACK BY
AD5248
ACK BY
AD5243
FRAME 2
FRAME 2
X
X
9
9
X
X
D7
D7
1
1
MASTER
X
X
D6
D6
X
X
D5
D5
RDAC REGISTER
RDAC REGISTER
X
X
FRAME 2
D4
FRAME 2
D4
SDA
AD5248
AD1
AD0
ACK BY
AD5243
ACK BY
AD5248
Figure 50. Multiple AD5248 Devices on One I
9
9
D3
D3
R
SCL
P
D7
D7
1
1
D2
D2
R
P
D6
D6
5V
D1
D1
D5
D5
SDA
AD5248
AD1
AD0
D0
D0
NO ACK
BY MASTER
DATA BYTE
DATA BYTE
NO ACK
BY MASTER
FRAME 3
D4
FRAME 3
D4
9
9
SCL
STOP BY
MASTER
STOP BY
MASTER
5V
D3
D3
5V
D2
D2
SDA
AD5248
AD1
AD0
D1
D1
D0
D0
SCL
ACK BY
AD5243
ACK BY
AD5248
2
9
9
C Bus
STOP BY
STOP BY
MASTER
MASTER
5V
SDA
AD5248
AD1
AD0
SCL
SDA
SCL