AD5259BRMZ10-R7 Analog Devices Inc, AD5259BRMZ10-R7 Datasheet - Page 5

• Manufacturer Part Number: AD5259BRMZ10-R7
• Description: IC,Digital Potentiometer,TSSOP,10PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD5259BRMZ10-R7

• Taps: 256
• Resistance (ohms): 10K
• Number Of Circuits: 1
• Temperature Coefficient: 500 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.3 V, 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resistance In Ohms: 10K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD5259EVAL - BOARD EVAL FOR AD5259 DGTL POT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS
V
Table 2.
Parameter
I
FLASH/EE MEMORY RELIABILITY
1
2
3
4
5
2
Standard I
During power-up, the output is momentarily preset to midscale before restoring EEPROM content.
Delay time after power-on PRESET prior to writing new EEPROM data.
Endurance is qualified to 100,000 cycles per JEDEC Std. 22 method A117, and is measured at –40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.
Retention lifetime equivalent at junction temperature (T
with junction temperature.
C INTERFACE TIMING
DD
CHARACTERISTICS
SCL Clock Frequency
t
t
t
t
t
Start Condition
t
t
t
t
t
EEPROM Data Storing Time
EEPROM Data Restoring Time at
EEPROM Data Restoring Time upon
EEPROM Data Rewritable Time
Endurance
Data Retention
BUF
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
F
R
SU;STO
= V
Fall Time of Both SDA and
Rise Time of Both SDA and
and Start
SCL Signals
SCL Signals
Power On
Restore Command
Bus Free Time Between Stop
Low Period of SCL Clock
High Period of SCL Clock
Setup Time for Repeated
Setup Time for Stop Condition
SCL
SDA
LOGIC
Hold Time (Repeated Start)
Data Setup Time
Data Hold Time
2
C mode operation guaranteed by design.
4
= 5 V ± 10% or 3 V ± 10%; V
2
P
5
1
t
1
2
S
t
2
3
t
3
A
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SCL
1
2
3
4
5
6
7
8
9
10
EEMEM_STORE
EEMEM_RESTORE1
EEMEM_RESTORE2
EEMEM_REWRITE
= V
8
t
8
J
DD
) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates
t
; V
9
B
Figure 4. I
= 0 V; −40°C < T
t
6
Conditions
After this period, the first clock pulse is
generated.
V
decoupling capacitors at V
V
DD
DD
t
4
t
Rev. B | Page 5 of 24
2
9
rise time dependent. Measure without
= 5 V.
C Interface Timing Diagram
A
< +85°C, unless otherwise noted.
t
7
DD
S
and GND.
t
5
t
2
Min
0
1.3
0.6
1.3
0.6
0.6
0
100
0.6
100
Typ
26
300
300
540
700
100
Max
400
0.9
300
300
P
t
10
AD5259
Unit
kHz
μs
μs
μs
μs
μs
μs
ns
ns
ns
μs
ms
μs
μs
μs
kCycles
Years