AD650BD Analog Devices Inc, AD650BD Datasheet - Page 8

• Manufacturer Part Number: AD650BD
• Description: Voltage / Frequency (V/F & F/V) Converter IC
• Manufacturer: Analog Devices Inc
• Type: Volt to Freq & Freq to Voltr

Specifications of AD650BD

• Mounting Type: Through Hole
• Package / Case: 14-DIP
• Frequency - Max: 1MHz
• Full Scale: ±150ppm/°C
• Linearity: ±0.1%
• Converter Function: VFC/FVC
• Full Scale Frequency: 1000
• Power Supply Requirement: Dual
• Single Supply Voltage (typ): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Single Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (min): ±9V
• Dual Supply Voltage (max): ±18V
• Operating Temperature (min): -25C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Package Type: SBCDIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD650
The positive input voltage develops a current (I
charges the integrator capacitor C
C
towards ground. When the integrator output voltage (Pin 1)
crosses the comparator threshold (–0.6 V) the comparator
triggers the one shot, whose time period, t
the one-shot capacitor C
Specifically, the one-shot time period is
The reset period is initiated as soon as the integrator output
voltage crosses the comparator threshold, and the integrator
ramps upward by an amount
After the reset period has ended, the device starts another
integration period, as shown in Figure 8, and starts ramping
downward again. The amount of time required to reach the
comparator threshold is given as
The output frequency is now given as
Note that C
transfer relation, but merely determines the amplitude of the
sawtooth signal out of the integrator.
One-Shot Timing
A key part of the preceding analysis is the one-shot time period
given in Equation 1. This time period can be broken down into
approximately 300 ns of propagation delay and a second time
segment dependent linearly on timing capacitor C
one shot is triggered, a voltage switch that holds Pin 6 at analog
ground is opened, allowing that voltage to change. An internal
0.5 mA current source connected to Pin 6 then draws its
current out of C
linearly. At approximately –3.4 V, the one shot resets itself,
thereby ending the timed period and starting the V/F
conversion cycle over again. The total one-shot time period can
be written mathematically as
substituting actual values quoted in Equation 5,
INT
, the output voltage of the integrator ramps downward
t
T
. 0
t
Δ
f
OS
OS
OUT
1
V
15
=
=
=
=
F
Δ
dV
=
C
dt
I
t
INT
×
V
OS
Δ
DISCHARGE
A
OS
t
Hz
OS
V
, the integration capacitor, has no effect on the
×
=
×
1
OS
C
+
dV
6
dt
C
C
OS
T
, causing the voltage at Pin 6 to decrease
t
8 .
OS
OS
INT
1
×
=
=
V
+
+
10
C
(
1
IN
C
t
4
T
t
OS
mA
I
OS
OS
INT
4 .
3
GATE
INT
N
/
.
sec
×
I
×
R
IN
(
1
10
IN
1
−
DELAY
mA
F /
mA
I
−
11
IN
+
F
INT
)
=
−
3
=
0 .
. As charge builds up on
I
t
IN
OS
×
)
10
⎛
⎜
⎜
⎝
1
OS
−
I
mA
7
IN
is determined by
sec
IN
−
1
= V
⎞
⎟
⎟
⎠
OS
. When the
IN
/R
IN
) that
Rev. D | Page 8 of 20
(1)
(2)
(3)
(4)
(5)
This simplifies into the timed period equation (see Equation 1).
COMPONENT SELECTION
Only four component values must be selected by the user. These
are input resistance R
and integration capacitor C
input voltage and full-scale frequency, while the last two are
determined by other circuit considerations.
Of the four components to be selected, R2 is the easiest to
define. As a pull-up resistor, it should be chosen to limit the
current through the output transistor to 8 mA if a TTL
maximum V
supply is used, R2 should be no smaller than 5 V/8 mA or
625 Ω. A larger value can be used if desired.
R
scale frequency to accommodate the given signal range. The swing
variable that is affected by the choice of R
The selection guides of Figure 9 and Figure 10 show this quite
graphically. In general, larger values of C
input currents (higher values of R
Figure 10, the implications of four different choices of R
shown. Although the selection guide is set up for a unipolar
configuration with a 0 V to 10 V input signal range, the results
can be extended to other configurations and input signal ranges.
For a full-scale frequency of 100 kHz (corresponding to 10 V
input), among the available choices R
gives the lowest nonlinearity, 0.0038%. In addition, the highest
frequency that gives the 20 ppm minimum nonlinearity is
approximately 33 kHz (40.2 kΩ and 1000 pF).
For input signal spans other than 10 V, the input resistance
must be scaled proportionately. For example, if 100 kΩ is called
out for a 0 V to 10 V span, 10 kΩ would be used with a 0 V to 1 V
span, or 200 kΩ with a ±10 V bipolar connection.
The last component to be selected is the integration capacitor
C
using the equation
When the proper value for C
architecture of the AD650 provides continuous integration
of the input signal, therefore, large amounts of noise and
interference can be rejected. If the output frequency is
measured by counting pulses during a constant gate period,
the integration provides infinite normal-mode rejection for
frequencies corresponding to the gate period and its harmonics.
However, if the integrator stage becomes saturated by an
excessively large noise pulse, then the continuous integration of
the signal is interrupted, allowing the noise to appear at the output.
IN
INT
and C
. In almost all cases, the best value for C
t
C
OS
INT
=
OS
=
−
−
are the only two parameters available to set the full-
10
3
OL
0
4 .
5 .
−
of 0.4 V is desired. For example, if a 5 V logic
f
V
×
4
MAX
F
10
×
/
C
sec
−
3
OS
IN
A
, timing capacitor C
(
1000
+
300
INT
INT
pF
. The first two determine the
×
10
is used, the charge balance
minimum
IN
−
9
) provide better linearity. In
IN
sec
= 20 kΩ and C
IN
OS
and C
)
OS
and lower full-scale
INT
, logic resistor R2,
OS
can be calculated
is nonlinearity.
OS
= 620 pF
IN
are
(6)
(7)