AD6623ASZ Analog Devices Inc, AD6623ASZ Datasheet - Page 42

• Manufacturer Part Number: AD6623ASZ
• Description: 4 Channel, 104 MSPS Digital TSP
• Manufacturer: Analog Devices Inc

Specifications of AD6623ASZ

• Applications: Transmit Signal Processor
• Interface: Serial
• Package / Case: 128-MQFP, 128-PQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD6623
APPLICATIONS
The AD6623 provides considerable flexibility for the control of
the synchronization, relative phasing, and scaling of the individual
channel inputs. Implementation of a multichannel transmitter
invariably begins with an analysis of the output spectrum that
must be generated.
Using the AD6623 to Process UMTS Carriers
The AD6623 may be used to process two UMTS carriers, each
with an output oversampling rate of 24 (i.e., 92.16 MSPS).
The AD6623 configuration used to accomplish this consists of
using two processing channels in parallel to process each UMTS
carrier. Please refer to the Using the AD6623 to Process Two
UMTS Carriers with 24 Oversampling, section.
Digital to Analog Converter (DAC) Selection
The selection of a high performance DAC depends on a number
of factors. The dynamic range of the DAC must be considered
from a noise and spectral purity perspective. The 14-bit AD9772A
is the best choice for overall bandwidth, noise, and spectral purity.
In order to minimize the complexity of the analog interpolation
filter which must follow the DAC, the sample rate of the master
clock is generally set to at least three times the maximum analog
frequency of interest.
In the case where a 15 MHz band of interest is to be up-converted
to RF, the lowest frequency might be 5 MHz and the upper band
edge at 20 MHz (offset from dc to afford the best image reject
filter after the first digital IF). The minimum sample rate would
be set to 65 MSPS.
Consideration must also be given to data rate of the incoming
data stream, interpolation factors, and the clock rate of the DSP.
Multiple TSP Operation
Each of the four Transmit Signal Processors (TSPs) of the AD6623
can adequately reject the interpolation images of narrow band-
width carriers such as AMPS, IS-136, GSM, EDGE, and PHS.
Wider bandwidth carriers such as IS-95 and IMT2000 require a
coordinated effort of multiple processing channels.
This section demonstrates how to coordinate multiple TSPs to
create wider bandwidth channels without sacrificing image
rejection. As an example, a UMTS carrier is modulated using
four TSP channels (an entire AD6623). The same principles
can be applied to different designs using more or fewer TSPs.
This section does not explore techniques for using multiple TSPs
to solve problems other than Serial Port or RCF throughput.
Designing filter coefficients and control settings for de-interleaved
TSPs is no harder than designing a filter for a single TSP. For
example, if four TSPs are to be used, simply divide the input
data rate by four and generate the filter as normal. For any
design, a better filter can always be realized by incrementing the
number of TSPs to be used. When it is time to program the
TSPs, only two small differences must be programmed. First,
each channel is configured with exactly the same filter, scalers,
modes and NCO frequency. Since each channel receives data at
one-quarter the data rate and in a staggered fashion, the Start
Hold-Off Counters must also be staggered (see “Programming
Multiple TSPs” section). Second, the phase offset of each NCO
must be set to match the demultiplexed ratio (in this example).
Thus the phase offset should be set to 90 degrees (16384 which
is one-quarter of a 16-bit register).
–42–
Determining the Number of TSPs to Use
There are three limitations of a single TSP that can be overcome
by deinterleaving an input stream into multiple TSPs: Serial Port
bandwidth, the time restriction to the RCF impulse response
length (NRCF), and the DMEM restriction to NRCF.
If the input sample rate is faster than the Serial Port can accept
data, the data can be de-interleaved into multiple Serial Ports.
Recalling from the Serial Port description, the SCLK frequency
(f
number of processing channels, SCLKdivider should be set as low
as possible to get the highest f
can accept.
A minimum of 32 SCLK cycles are required to accept an input
sample, so the minimum number of TSPs (NTSP) due to limited
Serial Port bandwidth is a function of the input sample rate (f
as shown in the equation below.
For example for a UMTS system, we will assume f
and the serial data source can drive data at 38.4 Mbps
(SCLKdivider = 0). To achieve f
N
of the Serial Port (This is TSP channels, not TSP ICs).
Multiple TSPs are also required if the RCF does not have enough
time or DMEM space to calculate the required RCF filter. Recalling
the maximum N
three restrictions to the RCF impulse response length, N
where:
De-interleaving the input data into multiple TSPs extends the
time restriction and may possibly extend the DMEM restriction,
but will not extend the CMEM restriction. De-interleaving the
input stream to multiple TSPs divides the input sample rate to
each TSP by the number of TSPs used (N
output rate fixed, L must be increased by a factor of N
extends the time restriction. This increase in L may be achieved by
increasing any one or more of L
normal limits. Achieving a larger L by increasing L
of L
In a UMTS example, N
f
L
the time restriction. Figure 42 shows an example RCF impulse
response which has a frequency response as shown in Figure 43
IN
SCLK
CIC
TSP
N
N
L
= 3.84 MHz, resulting in L = 80. Factoring L into L
f
SCLK
Time Restriction CMEM Restriction
CIC5
TSP
RCF
=
= 8, and L
is 3 with a Serial Clock f
) is determined by the equation below. To minimize the
L
≥
RCF
or L
=
≤
ceil
min
SCLKdivider
×
CIC2



L



32
CIC2
CIC
TAPS
1
2
DMEM Restriction
f
will relieves the DMEM restriction as well.
f
SCLK
CLK
, 16
×
5
= 1 results in a maximum N
– equation from the RCF description, are
×
f
IN
×
M
L



L
CIC
TSP
+ 1
CIC
RCF
2
2
SCLK
= 4, f
SCLK-
256
=
RCF
IN
N
= 52 MHz which is a limitation
= 3.84 MHz, the minimum



, L
TSP
CLK
that the serial data source
CIC5
f
IN
×
= 76.8 MHz, and
f
, or L
CLK
TSP
). To keep the
CIC2
CLK
RCF
within their
RCF
= 76.8 MHz,
= 40 due to
RCF
CH
instead
REV. A
RCF
, which
= 10,
(32)
(33)
.
IN
(30)
(31)
),