AD7224LR-18 Analog Devices Inc, AD7224LR-18 Datasheet - Page 6

• Manufacturer Part Number: AD7224LR-18
• Description: 8-BIT CMOS V-OUT DAC
• Manufacturer: Analog Devices Inc

Specifications of AD7224LR-18

• Rohs Status: RoHS non-compliant
• Settling Time: 7µs
• Number Of Bits: 8
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 75mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 18-SOIC (7.5mm Width)

AD7224
RESET LDAC
H
H
H
H
H
H
H
L
g
g
H = High State, L = Low State, X = Don’t Care.
All control inputs are level triggered.
The contents of both registers are reset by a low level on the
RESET line. With both registers transparent, the RESET line
functions like a zero override with the output brought to 0 V for
the duration of the RESET pulse. If both registers are latched, a
“LOW” pulse on RESET will latch all 0s into the registers and
the output remains at 0 V after the RESET line has returned
“HIGH”. The RESET line can be used to ensure power-up to
0 V on the AD7224 output and is also useful, when used as a
zero override, in system calibration cycles. Figure 3 shows the
input control logic for the AD7224.
SPECIFICATION RANGES
For the DAC to maintain specified accuracy, the reference volt-
age must be at least 4 V below the V
This voltage differential is required for correct generation of bias
voltages for the DAC switches.
With dual supply operation, the AD7224 has an extended V
range from +12 V
+16.5 V). Operation is also specified for a single V
supply of +15 V
Performance is specified over a wide range of reference voltages
from 2 V to (V
of standard reference generators to be used such as the AD580,
NOTES:
1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF V
2. TIMING MEASUREMENT REFERENCE LEVEL IS
LDAC
DATA
t r = t f = 20ns OVER V
IN
WR
CS
L
X
H
H
H
L
L
X
H
L
t
3
Figure 4. Write Cycle Timing Diagram
RESET
LDAC
DD
WR
CS
Figure 3. Input Control Logic
Table I. AD7224 Truth Table
– 4 V) with dual supplies. This allows a range
WR CS Function
L
H
X
L
g
L
g
X
H
L
5%.
t
t
1
2
t
VALID
DATA
5
5% to +15 V
DD
RANGE
t
L
X
H
L
L
H
H
X
H
L
6
t
4
With All Zeros
and Output Remains at Zero
Output Follows Input Data
Both Registers are Transparent
Both Registers are Latched
Both Registers are Latched
Input Register Transparent
Input Register Latched
DAC Register Transparent
DAC Register Latched
Both Registers Loaded
Both Register Latched With All Zeros
Both Registers are Transparent and
DD
10% (i.e., from +11.4 V to
t
3
V
INH
power supply voltage.
INPUT DATA
REGISTER
REGISTER
+ V
INPUT
2
DAC
INL
t
t
2
1
DD
power
t
4
DD
DD
.
–6–
a +2.5 V bandgap reference and the AD584, a precision +10 V
reference. Note that in order to achieve an output voltage range
of 0 V to +10 V, a nominal +15 V
required by the AD7224.
GROUND MANAGEMENT
AC or transient voltages between AGND and DGND can cause
noise at the analog output. This is especially true in micropro-
cessor systems where digital noise is prevalent. The simplest
method of ensuring that voltages at AGND and DGND are
equal is to tie AGND and DGND together at the AD7224. In
more complex systems where the AGND and DGND intertie is
on the backplane, it is recommended that two diodes be con-
nected in inverse parallel between the AD7224 AGND and
DGND pins (IN914 or equivalent).
Applying the AD7224
UNIPOLAR OUTPUT OPERATION
This is the basic mode of operation for the AD7224, with the
output voltage having the same positive polarity as V
AD7224 can be operated single supply (V
positive/negative supplies (see op-amp section which outlines
the advantages of having negative V
polar output operation are shown in Figure 5. The voltage at
V
observe this precaution may cause parasitic transistor action and
possible device destruction. The code table for unipolar output
operation is shown in Table II.
REF
must never be negative with respect to DGND. Failure to
Note: 1 LSB
DAC Register Contents
MSB
1 1 1 1
1 0 0 0
1 0 0 0
0 1 1 1
0 0 0 0
0 0 0 0
RESET
(8-BIT)
DATA
Figure 5. Unipolar Output Circuit
LDAC
DB0
DB7
WR
CS
Table III. Unipolar Code Table
1 1 1 1
0 0 0 1
0 0 0 0
1 1 1 1
0 0 0 1
0 0 0 0
LSB
V
REF
V
SS
2
V
DAC
REF
3
8
AGND
V
REF
Analog Output
0 V
SS
AD7224
5% power supply voltage is
V
V
V
V
V
). Connections for the uni-
REF
REF
REF
REF
REF
256
1
V
DD
SS
255
256
129
256
128
256
127
256
256
= AGND) or with
1
DGND
V
OUT
V
REF
REF
2
. The
REV. B