AD7294BSUZRL Analog Devices Inc, AD7294BSUZRL Datasheet - Page 38

• Manufacturer Part Number: AD7294BSUZRL
• Description: IC,Data Acquisition System,4-CHANNEL,12-BIT,TQFP,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: ADC, DACr

Specifications of AD7294BSUZRL

• Resolution (bits): 12 b
• Sampling Rate (per Second): 22.22k
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -55°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7294
Reading Data from an 8-Bit Register
Reading the contents from any of the 8-bit registers is a single
byte read operation, as shown in Figure 55. In this protocol, the
first part of the transaction writes to the register pointer. When
the register address has been set up, any number of reads can be
performed from that particular register without having to write
to the address pointer register again. When the required number
of reads is completed, the master should not acknowledge the final
byte. This tells the slave to stop transmitting, allowing a stop
condition to be asserted by the master. Further reads from this
register can be performed in a future transaction without
having to rewrite to the register pointer.
If a read from a different address is required, the relevant
register address has to be written to the address pointer register,
and again, any number of reads from this register can then be
performed. In the next example, the master device receives two
bytes from a slave device as follows:
1.
2.
3.
4.
5.
6.
7.
8.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
read bit (high).
The addressed slave device asserts an acknowledge
on SDA.
The master receives a data byte.
The master asserts an acknowledge on SDA.
The master receives another 8-bit data byte.
The master asserts a no acknowledge (NACK) on SDA to
inform the slave that the data transfer is complete.
The master asserts a stop condition on SDA, and the
transaction ends.
...
S
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
...
S
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
SLAVE ADDRESS
DATA<15:8>
DATA<7:0>
SLAVE ADDRESS
A
Figure 54. Reading Three Lots of Two Bytes of Data from the Conversion Result Register
A
S = START CONDITION
SR = REPEATED START
P = STOP CONDITION
A = ACKNOWLEDGE
A = NOT ACKNOWLEDGE
1
P
S = START CONDITION
SR = REPEATED START
P = STOP CONDITION
A = ACKNOWLEDGE
A = NOT ACKNOWLEDGE
DATA<7:0>
0
A
Figure 55. Reading Two Single Bytes of Data from a Selected Register
A
DATA<15:8>
REG POINTER
A
P
Rev. F | Page 38 of 48
A
A
DATA<7:0>
SR
Reading Two Bytes of Data from a 16-Bit Register
In this example, the master device reads three lots of two-byte
data from a slave device, but as many lots consisting of two-
bytes can be read as required. This protocol assumes that the
particular register address has been set up by a single byte write
operation to the address pointer register (see the previous read
example).
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. The master receives a second data byte.
11. The master asserts an acknowledge on SDA.
12. The master receives a data byte.
13. The master asserts an acknowledge on SDA.
14. The master receives a second data byte.
15. The master asserts a no acknowledge on SDA to notify the
16. The master asserts a stop condition on SDA to end the
SLAVE ADDRESS
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
read bit (high).
The addressed slave device asserts an acknowledge
on SDA.
The master receives a data byte.
The master asserts an acknowledge on SDA.
The master receives a second data byte.
The master asserts an acknowledge on SDA.
The master receives a data byte.
The master asserts an acknowledge on SDA.
slave that the data transfer is complete.
transaction.
A
DATA<15:8>
1
A
A
DATA<7:0>
DATA<7:0>
A
A
...
...